RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 02:52:53 +02:00
Code Issues Projects Releases Wiki Activity

[MIPS GlobalISel] Lower call for callee that is register

Browse Source 
Lower call for callee that is register for MIPS32.
Register should contain callee function address.

Differential Revision: https://reviews.llvm.org/D62585

llvm-svn: 362204
This commit is contained in:
Petar Avramovic 2019-05-31 08:06:17 +00:00
parent f7b00565ae
commit 0bb9750cc1
2 changed files with 28 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
lib/Target/Mips/MipsCallLowering.cpp
View File

@ -522,12 +522,8 @@ bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
MachineInstrBuilder CallSeqStart =
MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN);
// FIXME: Add support for pic calling sequences, long call sequences for O32,
// N32 and N64. First handle the case when Callee.isReg().
if (Callee.isReg())
return false;
MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(Mips::JAL);
MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(
Callee.isReg() ? Mips::JALRPseudo : Mips::JAL);
MIB.addDef(Mips::SP, RegState::Implicit);
MIB.add(Callee);
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
@ -573,6 +569,12 @@ bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
CallSeqStart.addImm(NextStackOffset).addImm(0);
MIRBuilder.insertInstr(MIB);
if (MIB->getOpcode() == Mips::JALRPseudo) {
const MipsSubtarget &STI =
static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
*STI.getRegBankInfo());
}
if (OrigRet.Reg) {

20
test/CodeGen/Mips/GlobalISel/irtranslator/call.ll
View File

@ -25,3 +25,23 @@ entry:
%doublez = add i32 %z, %z
ret i32 %doublez
}
define i32 @call_reg(i32 (i32, i32)* %f_ptr, i32 %x, i32 %y) {
; MIPS32-LABEL: name: call_reg
; MIPS32: bb.1.entry:
; MIPS32: liveins: $a0, $a1, $a2
; MIPS32: [[COPY:%[0-9]+]]:gpr32(p0) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[COPY1]](s32)
; MIPS32: $a1 = COPY [[COPY2]](s32)
; MIPS32: JALRPseudo [[COPY]](p0), csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $v0
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $v0 = COPY [[COPY3]](s32)
; MIPS32: RetRA implicit $v0
entry:
%call = call i32 %f_ptr(i32 %x, i32 %y)
ret i32 %call
}