From 0bbdb59c2533fc609028d817bf7c66ee78ef4f14 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Tue, 2 May 2017 18:05:36 +0000 Subject: [PATCH] [Hexagon] Remove unused validSubtarget TSFlags Patch by Colin LeMahieu. llvm-svn: 301952 --- lib/Target/Hexagon/HexagonInstrFormats.td | 16 ---------------- lib/Target/Hexagon/HexagonInstrFormatsV60.td | 8 -------- lib/Target/Hexagon/HexagonInstrInfo.cpp | 5 ----- lib/Target/Hexagon/HexagonInstrInfo.h | 1 - lib/Target/Hexagon/HexagonPseudo.td | 8 ++++---- .../Hexagon/MCTargetDesc/HexagonBaseInfo.h | 4 ---- .../MCTargetDesc/HexagonMCInstrInfo.cpp | 19 ------------------- .../Hexagon/MCTargetDesc/HexagonMCInstrInfo.h | 1 - 8 files changed, 4 insertions(+), 58 deletions(-) diff --git a/lib/Target/Hexagon/HexagonInstrFormats.td b/lib/Target/Hexagon/HexagonInstrFormats.td index 7d1da5c3ba2..709d64585c0 100644 --- a/lib/Target/Hexagon/HexagonInstrFormats.td +++ b/lib/Target/Hexagon/HexagonInstrFormats.td @@ -7,16 +7,6 @@ // //===----------------------------------------------------------------------===// -// Maintain list of valid subtargets for each instruction. -class SubTarget value> { - bits<6> Value = value; -} - -def HasAnySubT : SubTarget<0x3f>; // 111111 -def HasV5SubT : SubTarget<0x3e>; // 111110 -def HasV55SubT : SubTarget<0x3c>; // 111100 -def HasV60SubT : SubTarget<0x38>; // 111000 - // Addressing modes for load/store instructions class AddrModeType value> { bits<3> Value = value; @@ -131,12 +121,6 @@ class InstHexagon pattern, bits<2> opExtentAlign = 0; let TSFlags{34-33} = opExtentAlign; // Alignment exponent before extending. - // If an instruction is valid on a subtarget, set the corresponding - // bit from validSubTargets. - // By default, instruction is valid on all subtargets. - SubTarget validSubTargets = HasAnySubT; - let TSFlags{40-35} = validSubTargets.Value; - // Addressing mode for load/store instructions. AddrModeType addrMode = NoAddrMode; let TSFlags{43-41} = addrMode.Value; diff --git a/lib/Target/Hexagon/HexagonInstrFormatsV60.td b/lib/Target/Hexagon/HexagonInstrFormatsV60.td index 1c46ae77b6c..b913727972e 100644 --- a/lib/Target/Hexagon/HexagonInstrFormatsV60.td +++ b/lib/Target/Hexagon/HexagonInstrFormatsV60.td @@ -15,8 +15,6 @@ // Instruction Classes Definitions + //----------------------------------------------------------------------------// -let validSubTargets = HasV60SubT in -{ class CVI_VA_Resource pattern = [], string cstr = "", InstrItinClass itin = CVI_VA> @@ -184,10 +182,7 @@ class CVI_HIST_Resource : InstHexagon, OpcodeHexagon, Requires<[HasV60T, UseHVX]>; -} -let validSubTargets = HasV60SubT in -{ class CVI_VA_Resource1 pattern = [], string cstr = "", InstrItinClass itin = CVI_VA> @@ -205,6 +200,3 @@ class CVI_HIST_Resource1 : InstHexagon, Requires<[HasV60T, UseHVX]>; -} - - diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index b265a883da5..053d292bc8d 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -4139,11 +4139,6 @@ unsigned HexagonInstrInfo::getUnits(const MachineInstr &MI) const { return IS.getUnits(); } -unsigned HexagonInstrInfo::getValidSubTargets(const unsigned Opcode) const { - const uint64_t F = get(Opcode).TSFlags; - return (F >> HexagonII::validSubTargetPos) & HexagonII::validSubTargetMask; -} - // Calculate size of the basic block without debug instructions. unsigned HexagonInstrInfo::nonDbgBBSize(const MachineBasicBlock *BB) const { return nonDbgMICount(BB->instr_begin(), BB->instr_end()); diff --git a/lib/Target/Hexagon/HexagonInstrInfo.h b/lib/Target/Hexagon/HexagonInstrInfo.h index b268c7a2817..c3cbff3c4f0 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/lib/Target/Hexagon/HexagonInstrInfo.h @@ -424,7 +424,6 @@ public: unsigned getSize(const MachineInstr &MI) const; uint64_t getType(const MachineInstr &MI) const; unsigned getUnits(const MachineInstr &MI) const; - unsigned getValidSubTargets(const unsigned Opcode) const; /// getInstrTimingClassLatency - Compute the instruction latency of a given /// instruction using Timing Class information, if available. diff --git a/lib/Target/Hexagon/HexagonPseudo.td b/lib/Target/Hexagon/HexagonPseudo.td index 5a720e79456..17a131ab665 100644 --- a/lib/Target/Hexagon/HexagonPseudo.td +++ b/lib/Target/Hexagon/HexagonPseudo.td @@ -321,7 +321,7 @@ def LDriw_mod : LDInst<(outs ModRegs:$dst), // Vector load let Predicates = [HasV60T, UseHVX] in -let mayLoad = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in +let mayLoad = 1, hasSideEffects = 0 in class V6_LDInst pattern = [], string cstr = "", InstrItinClass itin = CVI_VM_LD, IType type = TypeCVI_VM_LD> @@ -329,7 +329,7 @@ let mayLoad = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in // Vector store let Predicates = [HasV60T, UseHVX] in -let mayStore = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in +let mayStore = 1, hasSideEffects = 0 in class V6_STInst pattern = [], string cstr = "", InstrItinClass itin = CVI_VM_ST, IType type = TypeCVI_VM_ST> @@ -415,7 +415,7 @@ let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in { // Vector load/store pseudos -let isPseudo = 1, isCodeGenOnly = 1, validSubTargets = HasV60SubT in +let isPseudo = 1, isCodeGenOnly = 1 in class STrivv_template : V6_STInst<(outs), (ins IntRegs:$addr, s32_0Imm:$off, RC:$src), "", []>; @@ -429,7 +429,7 @@ def PS_vstorerwu_ai_128B: STrivv_template, Requires<[HasV60T,UseHVXDbl]>; -let isPseudo = 1, isCodeGenOnly = 1, validSubTargets = HasV60SubT in +let isPseudo = 1, isCodeGenOnly = 1 in class LDrivv_template : V6_LDInst<(outs RC:$dst), (ins IntRegs:$addr, s32_0Imm:$off), "", []>; diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h index 53d8b04c50a..adb546dc214 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h @@ -128,10 +128,6 @@ namespace HexagonII { ExtentAlignPos = 33, ExtentAlignMask = 0x3, - // Valid subtargets - validSubTargetPos = 35, - validSubTargetMask = 0x3f, - // Addressing mode for load/store instructions. AddrModePos = 41, AddrModeMask = 0x7, diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp index 1c66bd96526..2d1113c25ea 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp @@ -384,25 +384,6 @@ unsigned HexagonMCInstrInfo::getType(MCInstrInfo const &MCII, return ((F >> HexagonII::TypePos) & HexagonII::TypeMask); } -int HexagonMCInstrInfo::getSubTarget(MCInstrInfo const &MCII, - MCInst const &MCI) { - const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; - - HexagonII::SubTarget Target = static_cast( - (F >> HexagonII::validSubTargetPos) & HexagonII::validSubTargetMask); - - switch (Target) { - default: - return Hexagon::ArchV4; - case HexagonII::HasV5SubT: - return Hexagon::ArchV5; - case HexagonII::HasV55SubT: - return Hexagon::ArchV55; - case HexagonII::HasV60SubT: - return Hexagon::ArchV60; - } -} - /// Return the slots this instruction can execute out of unsigned HexagonMCInstrInfo::getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h index 710ece71c53..7ccdf798fcb 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h @@ -152,7 +152,6 @@ MCOperand const &getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI); unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI); MCOperand const &getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI); -int getSubTarget(MCInstrInfo const &MCII, MCInst const &MCI); // Return the Hexagon ISA class for the insn. unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI);