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[ARM64] Check for proper immediate in shift/extend operands
llvm-svn: 208317
This commit is contained in:
Bradley Smith
parent
35d96c7f86
commit
0bcfb4a0bc
@ -56,8 +56,6 @@ private:
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bool parseCondCode(OperandVector &Operands, bool invertCondCode);
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int tryParseRegister();
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int tryMatchVectorRegister(StringRef &Kind, bool expected);
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bool parseOptionalShift(OperandVector &Operands);
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bool parseOptionalExtend(OperandVector &Operands);
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bool parseRegister(OperandVector &Operands);
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bool parseMemory(OperandVector &Operands);
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bool parseSymbolicImmVal(const MCExpr *&ImmVal);
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@ -87,6 +85,8 @@ private:
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/// }
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OperandMatchResultTy tryParseOptionalShift(OperandVector &Operands);
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OperandMatchResultTy tryParseOptionalExtend(OperandVector &Operands);
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OperandMatchResultTy tryParseNoIndexMemory(OperandVector &Operands);
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OperandMatchResultTy tryParseBarrierOperand(OperandVector &Operands);
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OperandMatchResultTy tryParseMRSSystemRegister(OperandVector &Operands);
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@ -2277,60 +2277,72 @@ bool ARM64AsmParser::parseCondCode(OperandVector &Operands,
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return false;
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}
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/// ParseOptionalShift - Some operands take an optional shift argument. Parse
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/// tryParseOptionalShift - Some operands take an optional shift argument. Parse
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/// them if present.
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bool ARM64AsmParser::parseOptionalShift(OperandVector &Operands) {
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ARM64AsmParser::OperandMatchResultTy
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ARM64AsmParser::tryParseOptionalShift(OperandVector &Operands) {
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const AsmToken &Tok = Parser.getTok();
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ARM64_AM::ShiftType ShOp = StringSwitch<ARM64_AM::ShiftType>(Tok.getString())
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std::string LowerID = Tok.getString().lower();
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ARM64_AM::ShiftType ShOp = StringSwitch<ARM64_AM::ShiftType>(LowerID)
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.Case("lsl", ARM64_AM::LSL)
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.Case("lsr", ARM64_AM::LSR)
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.Case("asr", ARM64_AM::ASR)
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.Case("ror", ARM64_AM::ROR)
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.Case("msl", ARM64_AM::MSL)
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.Case("LSL", ARM64_AM::LSL)
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.Case("LSR", ARM64_AM::LSR)
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.Case("ASR", ARM64_AM::ASR)
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.Case("ROR", ARM64_AM::ROR)
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.Case("MSL", ARM64_AM::MSL)
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.Default(ARM64_AM::InvalidShift);
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if (ShOp == ARM64_AM::InvalidShift)
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return true;
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return MatchOperand_NoMatch;
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SMLoc S = Tok.getLoc();
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Parser.Lex();
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// We expect a number here.
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bool Hash = getLexer().is(AsmToken::Hash);
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if (!Hash && getLexer().isNot(AsmToken::Integer))
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return TokError("immediate value expected for shifter operand");
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if (!Hash && getLexer().isNot(AsmToken::Integer)) {
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TokError("immediate value expected for shifter operand");
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return MatchOperand_ParseFail;
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}
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if (Hash)
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Parser.Lex(); // Eat the '#'.
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// Make sure we do actually have a number
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if (!Parser.getTok().is(AsmToken::Integer)) {
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Error(Parser.getTok().getLoc(),
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"expected integer shift amount");
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return MatchOperand_ParseFail;
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}
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SMLoc ExprLoc = getLoc();
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const MCExpr *ImmVal;
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if (getParser().parseExpression(ImmVal))
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return true;
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return MatchOperand_ParseFail;
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const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
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if (!MCE)
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return TokError("immediate value expected for shifter operand");
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if (!MCE) {
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TokError("immediate value expected for shifter operand");
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return MatchOperand_ParseFail;
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}
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if ((MCE->getValue() & 0x3f) != MCE->getValue())
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return Error(ExprLoc, "immediate value too large for shifter operand");
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if ((MCE->getValue() & 0x3f) != MCE->getValue()) {
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Error(ExprLoc, "immediate value too large for shifter operand");
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return MatchOperand_ParseFail;
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}
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SMLoc E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
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Operands.push_back(
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ARM64Operand::CreateShifter(ShOp, MCE->getValue(), S, E, getContext()));
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return false;
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return MatchOperand_Success;
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}
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/// parseOptionalExtend - Some operands take an optional extend argument. Parse
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/// tryParseOptionalExtend - Some operands take an optional extend argument. Parse
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/// them if present.
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bool ARM64AsmParser::parseOptionalExtend(OperandVector &Operands) {
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ARM64AsmParser::OperandMatchResultTy
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ARM64AsmParser::tryParseOptionalExtend(OperandVector &Operands) {
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const AsmToken &Tok = Parser.getTok();
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std::string LowerID = Tok.getString().lower();
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ARM64_AM::ExtendType ExtOp =
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StringSwitch<ARM64_AM::ExtendType>(Tok.getString())
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StringSwitch<ARM64_AM::ExtendType>(LowerID)
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.Case("uxtb", ARM64_AM::UXTB)
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.Case("uxth", ARM64_AM::UXTH)
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.Case("uxtw", ARM64_AM::UXTW)
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@ -2340,18 +2352,9 @@ bool ARM64AsmParser::parseOptionalExtend(OperandVector &Operands) {
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.Case("sxth", ARM64_AM::SXTH)
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.Case("sxtw", ARM64_AM::SXTW)
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.Case("sxtx", ARM64_AM::SXTX)
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.Case("UXTB", ARM64_AM::UXTB)
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.Case("UXTH", ARM64_AM::UXTH)
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.Case("UXTW", ARM64_AM::UXTW)
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.Case("UXTX", ARM64_AM::UXTX)
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.Case("LSL", ARM64_AM::UXTX) // Alias for UXTX
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.Case("SXTB", ARM64_AM::SXTB)
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.Case("SXTH", ARM64_AM::SXTH)
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.Case("SXTW", ARM64_AM::SXTW)
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.Case("SXTX", ARM64_AM::SXTX)
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.Default(ARM64_AM::InvalidExtend);
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if (ExtOp == ARM64_AM::InvalidExtend)
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return true;
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return MatchOperand_NoMatch;
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SMLoc S = Tok.getLoc();
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Parser.Lex();
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@ -2361,7 +2364,7 @@ bool ARM64AsmParser::parseOptionalExtend(OperandVector &Operands) {
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SMLoc E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
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Operands.push_back(
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ARM64Operand::CreateExtend(ExtOp, 0, S, E, getContext()));
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return false;
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return MatchOperand_Success;
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}
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bool Hash = getLexer().is(AsmToken::Hash);
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@ -2369,24 +2372,33 @@ bool ARM64AsmParser::parseOptionalExtend(OperandVector &Operands) {
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SMLoc E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
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Operands.push_back(
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ARM64Operand::CreateExtend(ExtOp, 0, S, E, getContext()));
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return false;
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return MatchOperand_Success;
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}
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if (Hash)
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Parser.Lex(); // Eat the '#'.
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// Make sure we do actually have a number
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if (!Parser.getTok().is(AsmToken::Integer)) {
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Error(Parser.getTok().getLoc(),
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"expected integer shift amount");
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return MatchOperand_ParseFail;
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}
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const MCExpr *ImmVal;
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if (getParser().parseExpression(ImmVal))
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return true;
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return MatchOperand_ParseFail;
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const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
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if (!MCE)
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return TokError("immediate value expected for extend operand");
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if (!MCE) {
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TokError("immediate value expected for extend operand");
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return MatchOperand_ParseFail;
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}
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SMLoc E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
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Operands.push_back(
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ARM64Operand::CreateExtend(ExtOp, MCE->getValue(), S, E, getContext()));
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return false;
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return MatchOperand_Success;
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}
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/// parseSysAlias - The IC, DC, AT, and TLBI instructions are simple aliases for
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@ -3216,12 +3228,16 @@ bool ARM64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
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return false;
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// This could be an optional "shift" operand.
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if (!parseOptionalShift(Operands))
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return false;
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OperandMatchResultTy GotShift = tryParseOptionalShift(Operands);
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// We can only continue if no tokens were eaten.
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if (GotShift != MatchOperand_NoMatch)
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return GotShift;
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// Or maybe it could be an optional "extend" operand.
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if (!parseOptionalExtend(Operands))
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return false;
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OperandMatchResultTy GotExtend = tryParseOptionalExtend(Operands);
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// We can only continue if no tokens were eaten.
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if (GotExtend != MatchOperand_NoMatch)
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return GotExtend;
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// This was not a register so parse other operands that start with an
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// identifier (like labels) as expressions and create them as immediates.
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