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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-26 04:32:44 +01:00

[Hexagon] Implement TargetTransformInfo for Hexagon

Author: Brendon Cahoon <bcahoon@codeaurora.org>
llvm-svn: 244089
This commit is contained in:
Krzysztof Parzyszek 2015-08-05 18:35:37 +00:00
parent 3b4a7e46d7
commit 0be5b0aea4
5 changed files with 155 additions and 7 deletions

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@ -42,6 +42,7 @@ add_llvm_target(HexagonCodeGen
HexagonSubtarget.cpp HexagonSubtarget.cpp
HexagonTargetMachine.cpp HexagonTargetMachine.cpp
HexagonTargetObjectFile.cpp HexagonTargetObjectFile.cpp
HexagonTargetTransformInfo.cpp
HexagonVLIWPacketizer.cpp HexagonVLIWPacketizer.cpp
) )

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@ -16,6 +16,7 @@
#include "HexagonISelLowering.h" #include "HexagonISelLowering.h"
#include "HexagonMachineScheduler.h" #include "HexagonMachineScheduler.h"
#include "HexagonTargetObjectFile.h" #include "HexagonTargetObjectFile.h"
#include "HexagonTargetTransformInfo.h"
#include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/Passes.h"
#include "llvm/IR/LegacyPassManager.h" #include "llvm/IR/LegacyPassManager.h"
#include "llvm/IR/Module.h" #include "llvm/IR/Module.h"
@ -107,11 +108,43 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: LLVMTargetMachine(T, "e-m:e-p:32:32-i1:32-i64:64-a:0-n32", TT, CPU, FS, : LLVMTargetMachine(T, "e-m:e-p:32:32-i1:32-i64:64-a:0-n32", TT, CPU, FS,
Options, RM, CM, OL), Options, RM, CM, OL),
TLOF(make_unique<HexagonTargetObjectFile>()), TLOF(make_unique<HexagonTargetObjectFile>()) {
Subtarget(TT, CPU, FS, *this) { initAsmInfo();
initAsmInfo();
} }
const HexagonSubtarget *
HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
AttributeSet FnAttrs = F.getAttributes();
Attribute CPUAttr =
FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
Attribute FSAttr =
FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
? CPUAttr.getValueAsString().str()
: TargetCPU;
std::string FS = !FSAttr.hasAttribute(Attribute::None)
? FSAttr.getValueAsString().str()
: TargetFS;
auto &I = SubtargetMap[CPU + FS];
if (!I) {
// This needs to be done before we create a new subtarget since any
// creation will depend on the TM and the code generation flags on the
// function that reside in TargetOptions.
resetTargetOptions(F);
I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
}
return I.get();
}
TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
return TargetIRAnalysis([this](Function &F) {
return TargetTransformInfo(HexagonTTIImpl(this, F));
});
}
HexagonTargetMachine::~HexagonTargetMachine() {} HexagonTargetMachine::~HexagonTargetMachine() {}
namespace { namespace {

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@ -24,7 +24,7 @@ class Module;
class HexagonTargetMachine : public LLVMTargetMachine { class HexagonTargetMachine : public LLVMTargetMachine {
std::unique_ptr<TargetLoweringObjectFile> TLOF; std::unique_ptr<TargetLoweringObjectFile> TLOF;
HexagonSubtarget Subtarget; mutable StringMap<std::unique_ptr<HexagonSubtarget>> SubtargetMap;
public: public:
HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU, HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
@ -32,12 +32,12 @@ public:
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
~HexagonTargetMachine() override; ~HexagonTargetMachine() override;
const HexagonSubtarget *getSubtargetImpl(const Function &) const override { const HexagonSubtarget *getSubtargetImpl(const Function &F) const override;
return &Subtarget;
}
static unsigned getModuleMatchQuality(const Module &M); static unsigned getModuleMatchQuality(const Module &M);
TargetPassConfig *createPassConfig(PassManagerBase &PM) override; TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
TargetIRAnalysis getTargetIRAnalysis() override;
TargetLoweringObjectFile *getObjFileLowering() const override { TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get(); return TLOF.get();

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@ -0,0 +1,44 @@
//===-- HexagonTargetTransformInfo.cpp - Hexagon specific TTI pass --------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
/// \file
/// This file implements a TargetTransformInfo analysis pass specific to the
/// Hexagon target machine. It uses the target's detailed information to provide
/// more precise answers to certain TTI queries, while letting the target
/// independent and default TTI implementations handle the rest.
///
//===----------------------------------------------------------------------===//
#include "HexagonTargetTransformInfo.h"
#include "llvm/Support/Debug.h"
using namespace llvm;
#define DEBUG_TYPE "hexagontti"
TargetTransformInfo::PopcntSupportKind
HexagonTTIImpl::getPopcntSupport(unsigned IntTyWidthInBit) const {
// Return Fast Hardware support as every input < 64 bits will be promoted
// to 64 bits.
return TargetTransformInfo::PSK_FastHardware;
}
// The Hexagon target can unroll loops with run-time trip counts.
void HexagonTTIImpl::getUnrollingPreferences(Loop *L,
TTI::UnrollingPreferences &UP) {
UP.Runtime = UP.Partial = true;
}
unsigned HexagonTTIImpl::getNumberOfRegisters(bool vector) const {
if (vector) {
// While its true that v60 has vector registers,
// we do not want to advertise it through this API
// as it enables LOOP and SLP vectorization.
return 0;
}
return 32;
}

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@ -0,0 +1,70 @@
//===-- HexagonTargetTransformInfo.cpp - Hexagon specific TTI pass --------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
/// \file
/// This file implements a TargetTransformInfo analysis pass specific to the
/// Hexagon target machine. It uses the target's detailed information to provide
/// more precise answers to certain TTI queries, while letting the target
/// independent and default TTI implementations handle the rest.
///
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONTARGETTRANSFORMINFO_H
#define LLVM_LIB_TARGET_HEXAGON_HEXAGONTARGETTRANSFORMINFO_H
#include "Hexagon.h"
#include "HexagonTargetMachine.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
#include "llvm/Target/TargetLowering.h"
namespace llvm {
class HexagonTTIImpl : public BasicTTIImplBase<HexagonTTIImpl> {
typedef BasicTTIImplBase<HexagonTTIImpl> BaseT;
typedef TargetTransformInfo TTI;
friend BaseT;
const HexagonSubtarget *ST;
const HexagonTargetLowering *TLI;
const HexagonSubtarget *getST() const { return ST; }
const HexagonTargetLowering *getTLI() const { return TLI; }
public:
explicit HexagonTTIImpl(const HexagonTargetMachine *TM, Function &F)
: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
TLI(ST->getTargetLowering()) {}
// Provide value semantics. MSVC requires that we spell all of these out.
HexagonTTIImpl(const HexagonTTIImpl &Arg)
: BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {}
HexagonTTIImpl(HexagonTTIImpl &&Arg)
: BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)),
TLI(std::move(Arg.TLI)) {}
/// \name Scalar TTI Implementations
/// @{
TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const;
// The Hexagon target can unroll loops with run-time trip counts.
void getUnrollingPreferences(Loop *L, TTI::UnrollingPreferences &UP);
/// @}
/// \name Vector TTI Implementations
/// @{
unsigned getNumberOfRegisters(bool vector) const;
/// @}
};
} // end namespace llvm
#endif