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[Hexagon] Implement TargetTransformInfo for Hexagon
Author: Brendon Cahoon <bcahoon@codeaurora.org> llvm-svn: 244089
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@ -42,6 +42,7 @@ add_llvm_target(HexagonCodeGen
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HexagonSubtarget.cpp
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HexagonTargetMachine.cpp
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HexagonTargetObjectFile.cpp
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HexagonTargetTransformInfo.cpp
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HexagonVLIWPacketizer.cpp
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)
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@ -16,6 +16,7 @@
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#include "HexagonISelLowering.h"
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#include "HexagonMachineScheduler.h"
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#include "HexagonTargetObjectFile.h"
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#include "HexagonTargetTransformInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/IR/Module.h"
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@ -107,11 +108,43 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
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CodeGenOpt::Level OL)
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: LLVMTargetMachine(T, "e-m:e-p:32:32-i1:32-i64:64-a:0-n32", TT, CPU, FS,
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Options, RM, CM, OL),
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TLOF(make_unique<HexagonTargetObjectFile>()),
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Subtarget(TT, CPU, FS, *this) {
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TLOF(make_unique<HexagonTargetObjectFile>()) {
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initAsmInfo();
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}
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const HexagonSubtarget *
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HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
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AttributeSet FnAttrs = F.getAttributes();
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Attribute CPUAttr =
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FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
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Attribute FSAttr =
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FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
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std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
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? CPUAttr.getValueAsString().str()
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: TargetCPU;
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std::string FS = !FSAttr.hasAttribute(Attribute::None)
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? FSAttr.getValueAsString().str()
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: TargetFS;
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auto &I = SubtargetMap[CPU + FS];
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if (!I) {
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// This needs to be done before we create a new subtarget since any
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// creation will depend on the TM and the code generation flags on the
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// function that reside in TargetOptions.
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resetTargetOptions(F);
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I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
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}
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return I.get();
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}
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TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
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return TargetIRAnalysis([this](Function &F) {
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return TargetTransformInfo(HexagonTTIImpl(this, F));
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});
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}
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HexagonTargetMachine::~HexagonTargetMachine() {}
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namespace {
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@ -24,7 +24,7 @@ class Module;
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class HexagonTargetMachine : public LLVMTargetMachine {
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std::unique_ptr<TargetLoweringObjectFile> TLOF;
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HexagonSubtarget Subtarget;
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mutable StringMap<std::unique_ptr<HexagonSubtarget>> SubtargetMap;
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public:
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HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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@ -32,12 +32,12 @@ public:
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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~HexagonTargetMachine() override;
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const HexagonSubtarget *getSubtargetImpl(const Function &) const override {
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return &Subtarget;
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}
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const HexagonSubtarget *getSubtargetImpl(const Function &F) const override;
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static unsigned getModuleMatchQuality(const Module &M);
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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TargetIRAnalysis getTargetIRAnalysis() override;
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TargetLoweringObjectFile *getObjFileLowering() const override {
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return TLOF.get();
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44
lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
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44
lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
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@ -0,0 +1,44 @@
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//===-- HexagonTargetTransformInfo.cpp - Hexagon specific TTI pass --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// \file
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/// This file implements a TargetTransformInfo analysis pass specific to the
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/// Hexagon target machine. It uses the target's detailed information to provide
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/// more precise answers to certain TTI queries, while letting the target
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/// independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#include "HexagonTargetTransformInfo.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "hexagontti"
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TargetTransformInfo::PopcntSupportKind
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HexagonTTIImpl::getPopcntSupport(unsigned IntTyWidthInBit) const {
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// Return Fast Hardware support as every input < 64 bits will be promoted
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// to 64 bits.
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return TargetTransformInfo::PSK_FastHardware;
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}
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// The Hexagon target can unroll loops with run-time trip counts.
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void HexagonTTIImpl::getUnrollingPreferences(Loop *L,
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TTI::UnrollingPreferences &UP) {
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UP.Runtime = UP.Partial = true;
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}
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unsigned HexagonTTIImpl::getNumberOfRegisters(bool vector) const {
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if (vector) {
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// While its true that v60 has vector registers,
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// we do not want to advertise it through this API
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// as it enables LOOP and SLP vectorization.
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return 0;
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}
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return 32;
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}
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70
lib/Target/Hexagon/HexagonTargetTransformInfo.h
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70
lib/Target/Hexagon/HexagonTargetTransformInfo.h
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@ -0,0 +1,70 @@
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//===-- HexagonTargetTransformInfo.cpp - Hexagon specific TTI pass --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// \file
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/// This file implements a TargetTransformInfo analysis pass specific to the
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/// Hexagon target machine. It uses the target's detailed information to provide
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/// more precise answers to certain TTI queries, while letting the target
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/// independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONTARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONTARGETTRANSFORMINFO_H
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#include "Hexagon.h"
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#include "HexagonTargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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class HexagonTTIImpl : public BasicTTIImplBase<HexagonTTIImpl> {
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typedef BasicTTIImplBase<HexagonTTIImpl> BaseT;
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typedef TargetTransformInfo TTI;
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friend BaseT;
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const HexagonSubtarget *ST;
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const HexagonTargetLowering *TLI;
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const HexagonSubtarget *getST() const { return ST; }
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const HexagonTargetLowering *getTLI() const { return TLI; }
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public:
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explicit HexagonTTIImpl(const HexagonTargetMachine *TM, Function &F)
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: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
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TLI(ST->getTargetLowering()) {}
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// Provide value semantics. MSVC requires that we spell all of these out.
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HexagonTTIImpl(const HexagonTTIImpl &Arg)
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: BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {}
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HexagonTTIImpl(HexagonTTIImpl &&Arg)
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: BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)),
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TLI(std::move(Arg.TLI)) {}
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/// \name Scalar TTI Implementations
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/// @{
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TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const;
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// The Hexagon target can unroll loops with run-time trip counts.
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void getUnrollingPreferences(Loop *L, TTI::UnrollingPreferences &UP);
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/// @}
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/// \name Vector TTI Implementations
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/// @{
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unsigned getNumberOfRegisters(bool vector) const;
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/// @}
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};
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} // end namespace llvm
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#endif
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