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Teach EmitLiveInCopies to omit copies for unused virtual registers,

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and to clean up unused incoming physregs from the live-in list.

llvm-svn: 106805
This commit is contained in:
Dan Gohman 2010-06-24 22:23:02 +00:00
parent bacc90a80d
commit 0be71f4660
3 changed files with 32 additions and 21 deletions
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39
lib/CodeGen/MachineRegisterInfo.cpp
View File

@ -182,21 +182,32 @@ MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
const TargetRegisterInfo &TRI,
const TargetInstrInfo &TII) {
// Emit the copies into the top of the block.
for (MachineRegisterInfo::livein_iterator LI = livein_begin(),
E = livein_end(); LI != E; ++LI)
if (LI->second) {
const TargetRegisterClass *RC = getRegClass(LI->second);
bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
LI->second, LI->first, RC, RC,
DebugLoc());
assert(Emitted && "Unable to issue a live-in copy instruction!\n");
(void) Emitted;
}
for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
if (LiveIns[i].second) {
if (use_empty(LiveIns[i].second)) {
// The livein has no uses. Drop it.
//
// It would be preferable to have isel avoid creating live-in
// records for unused arguments in the first place, but it's
// complicated by the debug info code for arguments.
LiveIns.erase(LiveIns.begin() + i);
--i; --e;
} else {
// Emit a copy.
const TargetRegisterClass *RC = getRegClass(LiveIns[i].second);
bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
LiveIns[i].second, LiveIns[i].first,
RC, RC, DebugLoc());
assert(Emitted && "Unable to issue a live-in copy instruction!\n");
(void) Emitted;
// Add function live-ins to entry block live-in set.
for (MachineRegisterInfo::livein_iterator I = livein_begin(),
E = livein_end(); I != E; ++I)
EntryMBB->addLiveIn(I->first);
// Add the register to the entry block live-in set.
EntryMBB->addLiveIn(LiveIns[i].first);
}
} else {
// Add the register to the entry block live-in set.
EntryMBB->addLiveIn(LiveIns[i].first);
}
}
void MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) {

8
test/CodeGen/ARM/long_shift.ll
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@ -23,10 +23,10 @@ define i32 @f1(i64 %x, i64 %y) {
define i32 @f2(i64 %x, i64 %y) {
; CHECK: f2
; CHECK: mov r0, r0, lsr r2
; CHECK-NEXT: rsb r12, r2, #32
; CHECK-NEXT: rsb r3, r2, #32
; CHECK-NEXT: sub r2, r2, #32
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: orr r0, r0, r1, lsl r12
; CHECK-NEXT: orr r0, r0, r1, lsl r3
; CHECK-NEXT: movge r0, r1, asr r2
%a = ashr i64 %x, %y
%b = trunc i64 %a to i32
@ -36,10 +36,10 @@ define i32 @f2(i64 %x, i64 %y) {
define i32 @f3(i64 %x, i64 %y) {
; CHECK: f3
; CHECK: mov r0, r0, lsr r2
; CHECK-NEXT: rsb r12, r2, #32
; CHECK-NEXT: rsb r3, r2, #32
; CHECK-NEXT: sub r2, r2, #32
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: orr r0, r0, r1, lsl r12
; CHECK-NEXT: orr r0, r0, r1, lsl r3
; CHECK-NEXT: movge r0, r1, lsr r2
%a = lshr i64 %x, %y
%b = trunc i64 %a to i32

6
test/CodeGen/X86/sse3.ll
View File

@ -63,10 +63,10 @@ define <8 x i16> @t4(<8 x i16> %A, <8 x i16> %B) nounwind {
ret <8 x i16> %tmp
; X64: t4:
; X64: pextrw $7, %xmm0, %eax
; X64: pshufhw $100, %xmm0, %xmm2
; X64: pinsrw $1, %eax, %xmm2
; X64: pshufhw $100, %xmm0, %xmm1
; X64: pinsrw $1, %eax, %xmm1
; X64: pextrw $1, %xmm0, %eax
; X64: movdqa %xmm2, %xmm0
; X64: movdqa %xmm1, %xmm0
; X64: pinsrw $4, %eax, %xmm0
; X64: ret
}