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AMDGPU: Remove pointless wrapper nodes for init.exec intrinsics

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llvm-svn: 371364
This commit is contained in:
Matt Arsenault 2019-09-09 05:49:52 +00:00
parent 8ad4b280ee
commit 0c069ba5b2
6 changed files with 7 additions and 28 deletions
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1
include/llvm/IR/IntrinsicsAMDGPU.td
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@ -175,6 +175,7 @@ def int_amdgcn_implicit_buffer_ptr :
// Set EXEC to the 64-bit value given.
// This is always moved to the beginning of the basic block.
// FIXME: Should be mangled for wave size.
def int_amdgcn_init_exec : Intrinsic<[],
[llvm_i64_ty], // 64-bit literal constant
[IntrConvergent, ImmArg<0>]>;

2
lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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@ -4351,8 +4351,6 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(KILL)
NODE_NAME_CASE(DUMMY_CHAIN)
case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break;
NODE_NAME_CASE(INIT_EXEC)
NODE_NAME_CASE(INIT_EXEC_FROM_INPUT)
NODE_NAME_CASE(INTERP_MOV)
NODE_NAME_CASE(INTERP_P1)
NODE_NAME_CASE(INTERP_P2)

2
lib/Target/AMDGPU/AMDGPUISelLowering.h
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@ -479,8 +479,6 @@ enum NodeType : unsigned {
BUILD_VERTICAL_VECTOR,
/// Pointer to the start of the shader's constant data.
CONST_DATA_PTR,
INIT_EXEC,
INIT_EXEC_FROM_INPUT,
INTERP_MOV,
INTERP_P1,
INTERP_P2,

9
lib/Target/AMDGPU/AMDGPUInstrInfo.td
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@ -330,15 +330,6 @@ def AMDGPUfdot2 : SDNode<"AMDGPUISD::FDOT2",
def AMDGPUperm : SDNode<"AMDGPUISD::PERM", AMDGPUDTIntTernaryOp, []>;
def AMDGPUinit_exec : SDNode<"AMDGPUISD::INIT_EXEC",
SDTypeProfile<0, 1, [SDTCisInt<0>]>,
[SDNPHasChain, SDNPInGlue]>;
def AMDGPUinit_exec_from_input : SDNode<"AMDGPUISD::INIT_EXEC_FROM_INPUT",
SDTypeProfile<0, 2,
[SDTCisInt<0>, SDTCisInt<1>]>,
[SDNPHasChain, SDNPInGlue]>;
def AMDGPUinterp_mov : SDNode<"AMDGPUISD::INTERP_MOV",
SDTypeProfile<1, 3, [SDTCisFP<0>]>,
[SDNPInGlue]>;

8
lib/Target/AMDGPU/SIISelLowering.cpp
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@ -6765,14 +6765,6 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
AMDGPUISD::EXPORT : AMDGPUISD::EXPORT_DONE;
return DAG.getNode(Opc, DL, Op->getVTList(), Ops);
}
case Intrinsic::amdgcn_init_exec: {
return DAG.getNode(AMDGPUISD::INIT_EXEC, DL, MVT::Other, Chain,
Op.getOperand(2));
}
case Intrinsic::amdgcn_init_exec_from_input: {
return DAG.getNode(AMDGPUISD::INIT_EXEC_FROM_INPUT, DL, MVT::Other, Chain,
Op.getOperand(2), Op.getOperand(3));
}
case Intrinsic::amdgcn_s_barrier: {
if (getTargetMachine().getOptLevel() > CodeGenOpt::None) {
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();

13
lib/Target/AMDGPU/SIInstructions.td
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@ -356,6 +356,7 @@ def SI_INIT_EXEC : SPseudoInstSI <
let WaveSizePredicate = isWave64;
}
// FIXME: Intrinsic should be mangled for wave size.
def SI_INIT_EXEC_LO : SPseudoInstSI <
(outs), (ins i32imm:$src), []> {
let Defs = [EXEC_LO];
@ -609,21 +610,19 @@ def : GCNPat <
>;
def : GCNPat <
(AMDGPUinit_exec i64:$src),
(SI_INIT_EXEC (as_i64imm $src))
> {
(int_amdgcn_init_exec i64:$src),
(SI_INIT_EXEC (as_i64imm $src))> {
let WaveSizePredicate = isWave64;
}
def : GCNPat <
(AMDGPUinit_exec i64:$src),
(SI_INIT_EXEC_LO (as_i32imm $src))
> {
(int_amdgcn_init_exec i64:$src),
(SI_INIT_EXEC_LO (as_i32imm $src))> {
let WaveSizePredicate = isWave32;
}
def : GCNPat <
(AMDGPUinit_exec_from_input i32:$input, i32:$shift),
(int_amdgcn_init_exec_from_input i32:$input, i32:$shift),
(SI_INIT_EXEC_FROM_INPUT (i32 $input), (as_i32imm $shift))
>;