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This patch adds support for microMIPS disassembler and disassembler make check tests.
llvm-svn: 190144
This commit is contained in:
Vladimir Medic
parent
e8f95344a5
commit
0c18f0f6ce
@ -53,12 +53,15 @@ protected:
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/// MipsDisassembler - a disasembler class for Mips32.
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class MipsDisassembler : public MipsDisassemblerBase {
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bool IsMicroMips;
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public:
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/// Constructor - Initializes the disassembler.
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///
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MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
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bool bigEndian) :
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MipsDisassemblerBase(STI, Info, bigEndian) {}
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MipsDisassemblerBase(STI, Info, bigEndian) {
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IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
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}
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/// getInstruction - See MCDisassembler.
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virtual DecodeStatus getInstruction(MCInst &instr,
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@ -182,6 +185,16 @@ static DecodeStatus DecodeMem(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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@ -251,7 +264,8 @@ static DecodeStatus readInstruction32(const MemoryObject ®ion,
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uint64_t address,
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uint64_t &size,
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uint32_t &insn,
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bool isBigEndian) {
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bool isBigEndian,
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bool IsMicroMips) {
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uint8_t Bytes[4];
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// We want to read exactly 4 Bytes of data.
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@ -269,10 +283,20 @@ static DecodeStatus readInstruction32(const MemoryObject ®ion,
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}
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else {
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// Encoded as a small-endian 32-bit word in the stream.
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insn = (Bytes[0] << 0) |
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(Bytes[1] << 8) |
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(Bytes[2] << 16) |
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(Bytes[3] << 24);
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// Little-endian byte ordering:
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// mips32r2: 4 | 3 | 2 | 1
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// microMIPS: 2 | 1 | 4 | 3
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if (IsMicroMips) {
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insn = (Bytes[2] << 0) |
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(Bytes[3] << 8) |
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(Bytes[0] << 16) |
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(Bytes[1] << 24);
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} else {
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insn = (Bytes[0] << 0) |
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(Bytes[1] << 8) |
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(Bytes[2] << 16) |
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(Bytes[3] << 24);
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}
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}
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return MCDisassembler::Success;
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@ -288,10 +312,21 @@ MipsDisassembler::getInstruction(MCInst &instr,
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uint32_t Insn;
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DecodeStatus Result = readInstruction32(Region, Address, Size,
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Insn, isBigEndian);
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Insn, isBigEndian, IsMicroMips);
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if (Result == MCDisassembler::Fail)
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return MCDisassembler::Fail;
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if (IsMicroMips) {
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// Calling the auto-generated decoder function.
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Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
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this, STI);
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if (Result != MCDisassembler::Fail) {
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Size = 4;
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return Result;
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}
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return MCDisassembler::Fail;
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}
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// Calling the auto-generated decoder function.
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Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
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this, STI);
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@ -313,7 +348,7 @@ Mips64Disassembler::getInstruction(MCInst &instr,
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uint32_t Insn;
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DecodeStatus Result = readInstruction32(Region, Address, Size,
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Insn, isBigEndian);
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Insn, isBigEndian, false);
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if (Result == MCDisassembler::Fail)
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return MCDisassembler::Fail;
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@ -470,6 +505,42 @@ static DecodeStatus DecodeMem(MCInst &Inst,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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int Offset = SignExtend32<12>(Insn & 0x0fff);
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unsigned Reg = fieldFromInstruction(Insn, 21, 5);
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unsigned Base = fieldFromInstruction(Insn, 16, 5);
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Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
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Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
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Inst.addOperand(MCOperand::CreateReg(Reg));
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Inst.addOperand(MCOperand::CreateReg(Base));
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Inst.addOperand(MCOperand::CreateImm(Offset));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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int Offset = SignExtend32<16>(Insn & 0xffff);
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unsigned Reg = fieldFromInstruction(Insn, 21, 5);
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unsigned Base = fieldFromInstruction(Insn, 16, 5);
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Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
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Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
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Inst.addOperand(MCOperand::CreateReg(Reg));
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Inst.addOperand(MCOperand::CreateReg(Base));
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Inst.addOperand(MCOperand::CreateImm(Offset));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFMem(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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@ -19,6 +19,7 @@ class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
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!strconcat(opstr, "\t$rt, $addr"),
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[(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
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NoItinerary, FrmI> {
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let DecoderMethod = "DecodeMemMMImm12";
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string Constraints = "$src = $rt";
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}
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@ -26,7 +27,9 @@ class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
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Operand MemOpnd>:
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InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
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!strconcat(opstr, "\t$rt, $addr"),
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[(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI>;
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[(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
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let DecoderMethod = "DecodeMemMMImm12";
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}
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let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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/// Arithmetic Instructions (ALU Immediate)
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@ -86,14 +89,16 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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SRLV_FM_MM<0xd0, 0>;
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/// Load and Store Instructions - aligned
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def LB_MM : Load<"lb", GPR32Opnd, sextloadi8>, MMRel, LW_FM_MM<0x7>;
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def LBu_MM : Load<"lbu", GPR32Opnd, zextloadi8>, MMRel, LW_FM_MM<0x5>;
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def LH_MM : Load<"lh", GPR32Opnd, sextloadi16>, MMRel, LW_FM_MM<0xf>;
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def LHu_MM : Load<"lhu", GPR32Opnd, zextloadi16>, MMRel, LW_FM_MM<0xd>;
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def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
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def SB_MM : Store<"sb", GPR32Opnd, truncstorei8>, MMRel, LW_FM_MM<0x6>;
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def SH_MM : Store<"sh", GPR32Opnd, truncstorei16>, MMRel, LW_FM_MM<0xe>;
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def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
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let DecoderMethod = "DecodeMemMMImm16" in {
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def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
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def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
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def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
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def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
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def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
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def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
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def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
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def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
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}
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/// Load and Store Instructions - unaligned
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def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
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149
test/MC/Disassembler/Mips/micromips.txt
Normal file
149
test/MC/Disassembler/Mips/micromips.txt
Normal file
@ -0,0 +1,149 @@
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# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mattr=micromips \
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# RUN: | FileCheck %s
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# CHECK: add $9, $6, $7
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0x00 0xe6 0x49 0x10
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# CHECK: addi $9, $6, 17767
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0x11 0x26 0x45 0x67
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# CHECK: addiu $9, $6, -15001
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0x31 0x26 0xc5 0x67
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# CHECK: addi $9, $6, 17767
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0x11 0x26 0x45 0x67
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# CHECK: addiu $9, $6, -15001
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0x31 0x26 0xc5 0x67
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# CHECK: addu $9, $6, $7
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0x00 0xe6 0x49 0x50
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# CHECK: sub $9, $6, $7
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0x00 0xe6 0x49 0x90
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# CHECK: subu $4, $3, $5
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0x00 0xa3 0x21 0xd0
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# CHECK: sub $6, $zero, $7
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0x00 0xe0 0x31 0x90
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# CHECK: subu $6, $zero, $7
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0x00 0xe0 0x31 0xd0
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# CHECK: addu $7, $8, $zero
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0x00 0x08 0x39 0x50
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# CHECK: slt $3, $3, $5
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0x00 0xa3 0x1b 0x50
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# CHECK: slti $3, $3, 103
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0x90 0x63 0x00 0x67
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# CHECK: slti $3, $3, 103
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0x90 0x63 0x00 0x67
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# CHECK: sltiu $3, $3, 103
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0xb0 0x63 0x00 0x67
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# CHECK: sltu $3, $3, $5
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0x00 0xa3 0x1b 0x90
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# CHECK: and $9, $6, $7
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0x00 0xe6 0x4a 0x50
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# CHECK: andi $9, $6, 17767
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0xd1 0x26 0x45 0x67
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# CHECK: andi $9, $6, 17767
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0xd1 0x26 0x45 0x67
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# CHECK: or $3, $4, $5
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0x00 0xa4 0x1a 0x90
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# CHECK: ori $9, $6, 17767
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0x51 0x26 0x45 0x67
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# CHECK: xor $3, $3, $5
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0x00 0xa3 0x1b 0x10
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# CHECK: xori $9, $6, 17767
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0x71 0x26 0x45 0x67
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# CHECK: xori $9, $6, 17767
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0x71 0x26 0x45 0x67
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# CHECK: nor $9, $6, $7
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0x00 0xe6 0x4a 0xd0
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# CHECK: not $7, $8
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0x00 0x08 0x3a 0xd0
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# CHECK: mul $9, $6, $7
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0x00 0xe6 0x4a 0x10
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# CHECK: mult $9, $7
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0x00 0xe9 0x8b 0x3c
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# CHECK: multu $9, $7
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0x00 0xe9 0x9b 0x3c
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# CHECK: sll $4, $3, 7
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0x00 0x83 0x38 0x00
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# CHECK: sllv $2, $3, $5
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0x00 0x65 0x10 0x10
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# CHECK: sra $4, $3, 7
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0x00 0x83 0x38 0x80
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# CHECK: srav $2, $3, $5
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0x00 0x65 0x10 0x90
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# CHECK: srl $4, $3, 7
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0x00 0x83 0x38 0x40
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# CHECK: srlv $2, $3, $5
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0x00 0x65 0x10 0x50
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# CHECK: rotr $9, $6, 7
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0x01 0x26 0x38 0xc0
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# CHECK: rotrv $9, $6, $7
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0x00 0xc7 0x48 0xd0
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# CHECK: lb $5, 8($4)
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0x1c 0xa4 0x00 0x08
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# CHECK: lbu $6, 8($4)
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0x14 0xc4 0x00 0x08
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# CHECK: lh $2, 8($4)
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0x3c 0x44 0x00 0x08
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# CHECK: lhu $4, 8($2)
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0x34 0x82 0x00 0x08
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# CHECK: lw $6, 4($5)
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0xfc 0xc5 0x00 0x04
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# CHECK: sb $5, 8($4)
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0x18 0xa4 0x00 0x08
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# CHECK: sh $2, 8($4)
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0x38 0x44 0x00 0x08
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# CHECK: sw $5, 4($6)
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0xf8 0xa6 0x00 0x04
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# CHECK: lwl $4, 16($5)
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0x60 0x85 0x00 0x10
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# CHECK: lwr $4, 16($5)
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0x60 0x85 0x10 0x10
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# CHECK: swl $4, 16($5)
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0x60 0x85 0x80 0x10
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# CHECK: swr $4, 16($5)
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0x60 0x85 0x90 0x10
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149
test/MC/Disassembler/Mips/micromips_le.txt
Normal file
149
test/MC/Disassembler/Mips/micromips_le.txt
Normal file
@ -0,0 +1,149 @@
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# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mattr=micromips \
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# RUN: | FileCheck %s
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# CHECK: add $9, $6, $7
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0xe6 0x00 0x10 0x49
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# CHECK: addi $9, $6, 17767
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0x26 0x11 0x67 0x45
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# CHECK: addiu $9, $6, -15001
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0x26 0x31 0x67 0xc5
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# CHECK: addi $9, $6, 17767
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0x26 0x11 0x67 0x45
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# CHECK: addiu $9, $6, -15001
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0x26 0x31 0x67 0xc5
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# CHECK: addu $9, $6, $7
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0xe6 0x00 0x50 0x49
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# CHECK: sub $9, $6, $7
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0xe6 0x00 0x90 0x49
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# CHECK: subu $4, $3, $5
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0xa3 0x00 0xd0 0x21
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# CHECK: sub $6, $zero, $7
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0xe0 0x00 0x90 0x31
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# CHECK: subu $6, $zero, $7
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0xe0 0x00 0xd0 0x31
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# CHECK: addu $7, $8, $zero
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0x08 0x00 0x50 0x39
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# CHECK: slt $3, $3, $5
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0xa3 0x00 0x50 0x1b
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# CHECK: slti $3, $3, 103
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0x63 0x90 0x67 0x00
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# CHECK: slti $3, $3, 103
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0x63 0x90 0x67 0x00
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# CHECK: sltiu $3, $3, 103
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0x63 0xb0 0x67 0x00
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# CHECK: sltu $3, $3, $5
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0xa3 0x00 0x90 0x1b
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# CHECK: and $9, $6, $7
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0xe6 0x00 0x50 0x4a
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# CHECK: andi $9, $6, 17767
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0x26 0xd1 0x67 0x45
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# CHECK: andi $9, $6, 17767
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0x26 0xd1 0x67 0x45
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# CHECK: or $3, $4, $5
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0xa4 0x00 0x90 0x1a
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# CHECK: ori $9, $6, 17767
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0x26 0x51 0x67 0x45
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# CHECK: xor $3, $3, $5
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0xa3 0x00 0x10 0x1b
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# CHECK: xori $9, $6, 17767
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0x26 0x71 0x67 0x45
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# CHECK: xori $9, $6, 17767
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0x26 0x71 0x67 0x45
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# CHECK: nor $9, $6, $7
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0xe6 0x00 0xd0 0x4a
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# CHECK: not $7, $8
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0x08 0x00 0xd0 0x3a
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# CHECK: mul $9, $6, $7
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0xe6 0x00 0x10 0x4a
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# CHECK: mult $9, $7
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0xe9 0x00 0x3c 0x8b
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# CHECK: multu $9, $7
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0xe9 0x00 0x3c 0x9b
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# CHECK: sll $4, $3, 7
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0x83 0x00 0x00 0x38
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# CHECK: sllv $2, $3, $5
|
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0x65 0x00 0x10 0x10
|
||||
|
||||
# CHECK: sra $4, $3, 7
|
||||
0x83 0x00 0x80 0x38
|
||||
|
||||
# CHECK: srav $2, $3, $5
|
||||
0x65 0x00 0x90 0x10
|
||||
|
||||
# CHECK: srl $4, $3, 7
|
||||
0x83 0x00 0x40 0x38
|
||||
|
||||
# CHECK: srlv $2, $3, $5
|
||||
0x65 0x00 0x50 0x10
|
||||
|
||||
# CHECK: rotr $9, $6, 7
|
||||
0x26 0x01 0xc0 0x38
|
||||
|
||||
# CHECK: rotrv $9, $6, $7
|
||||
0xc7 0x00 0xd0 0x48
|
||||
|
||||
# CHECK: lb $5, 8($4)
|
||||
0xa4 0x1c 0x08 0x00
|
||||
|
||||
# CHECK: lbu $6, 8($4)
|
||||
0xc4 0x14 0x08 0x00
|
||||
|
||||
# CHECK: lh $2, 8($4)
|
||||
0x44 0x3c 0x08 0x00
|
||||
|
||||
# CHECK: lhu $4, 8($2)
|
||||
0x82 0x34 0x08 0x00
|
||||
|
||||
# CHECK: lw $6, 4($5)
|
||||
0xc5 0xfc 0x04 0x00
|
||||
|
||||
# CHECK: sb $5, 8($4)
|
||||
0xa4 0x18 0x08 0x00
|
||||
|
||||
# CHECK: sh $2, 8($4)
|
||||
0x44 0x38 0x08 0x00
|
||||
|
||||
# CHECK: sw $5, 4($6)
|
||||
0xa6 0xf8 0x04 0x00
|
||||
|
||||
# CHECK: lwl $4, 16($5)
|
||||
0x85 0x60 0x10 0x00
|
||||
|
||||
# CHECK: lwr $4, 16($5)
|
||||
0x85 0x60 0x10 0x10
|
||||
|
||||
# CHECK: swl $4, 16($5)
|
||||
0x85 0x60 0x10 0x80
|
||||
|
||||
# CHECK: swr $4, 16($5)
|
||||
0x85 0x60 0x10 0x90
|
||||
Loading…
Reference in New Issue
Block a user