diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp index f026d58383d..5cee2070f18 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -2100,7 +2100,6 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, setOperationAction(ISD::MUL, T, Custom); setOperationAction(ISD::MULHS, T, Custom); setOperationAction(ISD::MULHU, T, Custom); - setOperationAction(ISD::SETCC, T, Custom); setOperationAction(ISD::BUILD_VECTOR, T, Custom); setOperationAction(ISD::INSERT_SUBVECTOR, T, Custom); setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom); @@ -2116,6 +2115,14 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, setOperationAction(ISD::SHL, T, Custom); setOperationAction(ISD::SRL, T, Custom); } + + setCondCodeAction(ISD::SETNE, T, Expand); + setCondCodeAction(ISD::SETLE, T, Expand); + setCondCodeAction(ISD::SETGE, T, Expand); + setCondCodeAction(ISD::SETLT, T, Expand); + setCondCodeAction(ISD::SETULE, T, Expand); + setCondCodeAction(ISD::SETUGE, T, Expand); + setCondCodeAction(ISD::SETULT, T, Expand); } for (MVT T : LegalV) { @@ -2303,6 +2310,8 @@ const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const { case HexagonISD::P2D: return "HexagonISD::P2D"; case HexagonISD::V2Q: return "HexagonISD::V2Q"; case HexagonISD::Q2V: return "HexagonISD::Q2V"; + case HexagonISD::QTRUE: return "HexagonISD::QTRUE"; + case HexagonISD::QFALSE: return "HexagonISD::QFALSE"; case HexagonISD::TYPECAST: return "HexagonISD::TYPECAST"; case HexagonISD::OP_END: break; } diff --git a/lib/Target/Hexagon/HexagonISelLowering.h b/lib/Target/Hexagon/HexagonISelLowering.h index 59b39b7544b..200f7253f81 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.h +++ b/lib/Target/Hexagon/HexagonISelLowering.h @@ -73,6 +73,8 @@ namespace HexagonISD { // [*] The equivalence is defined as "Q <=> (V != 0)", // where the != operation compares bytes. // Note: V != 0 is implemented as V >u 0. + QTRUE, + QFALSE, VZERO, TYPECAST, // No-op that's used to convert between different legal // types in a register. diff --git a/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp index 9c0c3e0e2de..571b78ee94e 100644 --- a/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp +++ b/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp @@ -324,6 +324,18 @@ HexagonTargetLowering::buildHvxVectorPred(ArrayRef Values, unsigned HwLen = Subtarget.getVectorLength(); assert(VecLen <= HwLen || VecLen == 8*HwLen); SmallVector Bytes; + bool AllT = true, AllF = true; + + auto IsTrue = [] (SDValue V) { + if (const auto *N = dyn_cast(V.getNode())) + return !N->isNullValue(); + return false; + }; + auto IsFalse = [] (SDValue V) { + if (const auto *N = dyn_cast(V.getNode())) + return N->isNullValue(); + return false; + }; if (VecLen <= HwLen) { // In the hardware, each bit of a vector predicate corresponds to a byte @@ -332,8 +344,11 @@ HexagonTargetLowering::buildHvxVectorPred(ArrayRef Values, assert(HwLen % VecLen == 0); unsigned BitBytes = HwLen / VecLen; for (SDValue V : Values) { + AllT &= IsTrue(V); + AllF &= IsFalse(V); + SDValue Ext = !V.isUndef() ? DAG.getZExtOrTrunc(V, dl, MVT::i8) - : DAG.getConstant(0, dl, MVT::i8); + : DAG.getUNDEF(MVT::i8); for (unsigned B = 0; B != BitBytes; ++B) Bytes.push_back(Ext); } @@ -349,8 +364,11 @@ HexagonTargetLowering::buildHvxVectorPred(ArrayRef Values, break; } SDValue F = Values[I+B]; + AllT &= IsTrue(F); + AllF &= IsFalse(F); + SDValue Ext = (B < 8) ? DAG.getZExtOrTrunc(F, dl, MVT::i8) - : DAG.getConstant(0, dl, MVT::i8); + : DAG.getUNDEF(MVT::i8); Bytes.push_back(Ext); // Verify that the rest of values in the group are the same as the // first. @@ -359,6 +377,11 @@ HexagonTargetLowering::buildHvxVectorPred(ArrayRef Values, } } + if (AllT) + return DAG.getNode(HexagonISD::QTRUE, dl, VecTy); + if (AllF) + return DAG.getNode(HexagonISD::QFALSE, dl, VecTy); + MVT ByteTy = MVT::getVectorVT(MVT::i8, HwLen); SDValue ByteVec = buildHvxVectorReg(Bytes, dl, ByteTy, DAG); return DAG.getNode(HexagonISD::V2Q, dl, VecTy, ByteVec); @@ -1013,6 +1036,7 @@ HexagonTargetLowering::LowerHvxMulh(SDValue Op, SelectionDAG &DAG) const { SDValue HexagonTargetLowering::LowerHvxSetCC(SDValue Op, SelectionDAG &DAG) const { + MVT ResTy = ty(Op); MVT VecTy = ty(Op.getOperand(0)); assert(VecTy == ty(Op.getOperand(1))); unsigned HwLen = Subtarget.getVectorLength(); @@ -1024,78 +1048,14 @@ HexagonTargetLowering::LowerHvxSetCC(SDValue Op, SelectionDAG &DAG) const { if (VecTy.getSizeInBits() == 16*HwLen) { VectorPair P0 = opSplit(Op.getOperand(0), dl, DAG); VectorPair P1 = opSplit(Op.getOperand(1), dl, DAG); - MVT HalfTy = typeSplit(VecTy).first; + MVT HalfTy = typeSplit(ResTy).first; SDValue V0 = DAG.getSetCC(dl, HalfTy, P0.first, P1.first, CC); SDValue V1 = DAG.getSetCC(dl, HalfTy, P0.second, P1.second, CC); - return DAG.getNode(ISD::CONCAT_VECTORS, dl, ty(Op), V1, V0); + return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, V1, V0); } - bool Negate = false, Swap = false; - - // HVX has instructions for SETEQ, SETGT, SETUGT. The other comparisons - // can be arranged as operand-swapped/negated versions of these. Since - // the generated code will have the original CC expressed as - // (negate (swap-op NewCmp)), - // the condition code for the NewCmp should be calculated from the original - // CC by applying these operations in the reverse order. - // - // This could also be done through setCondCodeAction, but for negation it - // uses a xor with a vector of -1s, which it obtains from BUILD_VECTOR. - // That is far too expensive for what can be done with a single instruction. - - switch (CC) { - case ISD::SETNE: // !eq - case ISD::SETLE: // !gt - case ISD::SETGE: // !lt - case ISD::SETULE: // !ugt - case ISD::SETUGE: // !ult - CC = ISD::getSetCCInverse(CC, true); - Negate = true; - break; - default: - break; - } - - switch (CC) { - case ISD::SETLT: // swap gt - case ISD::SETULT: // swap ugt - CC = ISD::getSetCCSwappedOperands(CC); - Swap = true; - break; - default: - break; - } - - assert(CC == ISD::SETEQ || CC == ISD::SETGT || CC == ISD::SETUGT); - - MVT ElemTy = VecTy.getVectorElementType(); - unsigned ElemWidth = ElemTy.getSizeInBits(); - assert(isPowerOf2_32(ElemWidth)); - - auto getIdx = [] (unsigned Code) { - static const unsigned Idx[] = { ISD::SETEQ, ISD::SETGT, ISD::SETUGT }; - for (unsigned I = 0, E = array_lengthof(Idx); I != E; ++I) - if (Code == Idx[I]) - return I; - llvm_unreachable("Unhandled CondCode"); - }; - - static unsigned OpcTable[3][3] = { - // SETEQ SETGT, SETUGT - /* Byte */ { Hexagon::V6_veqb, Hexagon::V6_vgtb, Hexagon::V6_vgtub }, - /* Half */ { Hexagon::V6_veqh, Hexagon::V6_vgth, Hexagon::V6_vgtuh }, - /* Word */ { Hexagon::V6_veqw, Hexagon::V6_vgtw, Hexagon::V6_vgtuw } - }; - - unsigned CmpOpc = OpcTable[Log2_32(ElemWidth)-3][getIdx(CC)]; - - MVT ResTy = ty(Op); - SDValue OpL = Swap ? Op.getOperand(1) : Op.getOperand(0); - SDValue OpR = Swap ? Op.getOperand(0) : Op.getOperand(1); - SDValue CmpV = getInstr(CmpOpc, dl, ResTy, {OpL, OpR}, DAG); - return Negate ? getInstr(Hexagon::V6_pred_not, dl, ResTy, {CmpV}, DAG) - : CmpV; + return SDValue(); } SDValue diff --git a/lib/Target/Hexagon/HexagonPatterns.td b/lib/Target/Hexagon/HexagonPatterns.td index 06e23e24991..31aac6c1e23 100644 --- a/lib/Target/Hexagon/HexagonPatterns.td +++ b/lib/Target/Hexagon/HexagonPatterns.td @@ -2993,8 +2993,14 @@ def Combinev: OutPatFrag<(ops node:$Rs, node:$Rt), def LoVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_lo)>; def HiVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_hi)>; -def HexagonVZERO: SDNode<"HexagonISD::VZERO", SDTVecLeaf>; -def vzero: PatFrag<(ops), (HexagonVZERO)>; +def HexagonVZERO: SDNode<"HexagonISD::VZERO", SDTVecLeaf>; +def HexagonQTRUE: SDNode<"HexagonISD::QTRUE", SDTVecLeaf>; +def HexagonQFALSE: SDNode<"HexagonISD::QFALSE", SDTVecLeaf>; +def vzero: PatFrag<(ops), (HexagonVZERO)>; +def qtrue: PatFrag<(ops), (HexagonQTRUE)>; +def qfalse: PatFrag<(ops), (HexagonQFALSE)>; + +def qnot: PatFrag<(ops node:$Qs), (xor node:$Qs, qtrue)>; def VSxtb: OutPatFrag<(ops node:$Vs), (V6_vunpackb $Vs)>; def VSxth: OutPatFrag<(ops node:$Vs), (V6_vunpackh $Vs)>; @@ -3074,6 +3080,13 @@ let Predicates = [UseHVX] in { def: Pat<(vselect HQ32:$Qu, HVI32:$Vs, HVI32:$Vt), (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>; + def: Pat<(vselect (qnot HQ8:$Qu), HVI8:$Vs, HVI8:$Vt), + (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>; + def: Pat<(vselect (qnot HQ16:$Qu), HVI16:$Vs, HVI16:$Vt), + (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>; + def: Pat<(vselect (qnot HQ32:$Qu), HVI32:$Vs, HVI32:$Vt), + (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>; + def: Pat<(VecPI16 (sext HVI8:$Vs)), (VSxtb $Vs)>; def: Pat<(VecPI32 (sext HVI16:$Vs)), (VSxth $Vs)>; def: Pat<(VecPI16 (zext HVI8:$Vs)), (VZxtb $Vs)>; @@ -3122,6 +3135,32 @@ let Predicates = [UseHVX] in { def: Pat<(srl HVI16:$Vs, HVI16:$Vt), (V6_vlsrhv HvxVR:$Vs, HvxVR:$Vt)>; def: Pat<(srl HVI32:$Vs, HVI32:$Vt), (V6_vlsrwv HvxVR:$Vs, HvxVR:$Vt)>; + def: Pat<(vnot HQ8:$Qs), (V6_pred_not HvxQR:$Qs)>; + def: Pat<(vnot HQ16:$Qs), (V6_pred_not HvxQR:$Qs)>; + def: Pat<(vnot HQ32:$Qs), (V6_pred_not HvxQR:$Qs)>; + def: Pat<(qnot HQ8:$Qs), (V6_pred_not HvxQR:$Qs)>; + def: Pat<(qnot HQ16:$Qs), (V6_pred_not HvxQR:$Qs)>; + def: Pat<(qnot HQ32:$Qs), (V6_pred_not HvxQR:$Qs)>; + + def: Pat<(VecQ8 (seteq HVI8:$Vs, HVI8:$Vt)), + (V6_veqb HvxVR:$Vs, HvxVR:$Vt)>; + def: Pat<(VecQ8 (setgt HVI8:$Vs, HVI8:$Vt)), + (V6_vgtb HvxVR:$Vs, HvxVR:$Vt)>; + def: Pat<(VecQ8 (setugt HVI8:$Vs, HVI8:$Vt)), + (V6_vgtub HvxVR:$Vs, HvxVR:$Vt)>; + def: Pat<(VecQ16 (seteq HVI16:$Vs, HVI16:$Vt)), + (V6_veqh HvxVR:$Vs, HvxVR:$Vt)>; + def: Pat<(VecQ16 (setgt HVI16:$Vs, HVI16:$Vt)), + (V6_vgth HvxVR:$Vs, HvxVR:$Vt)>; + def: Pat<(VecQ16 (setugt HVI16:$Vs, HVI16:$Vt)), + (V6_vgtuh HvxVR:$Vs, HvxVR:$Vt)>; + def: Pat<(VecQ32 (seteq HVI32:$Vs, HVI32:$Vt)), + (V6_veqw HvxVR:$Vs, HvxVR:$Vt)>; + def: Pat<(VecQ32 (setgt HVI32:$Vs, HVI32:$Vt)), + (V6_vgtw HvxVR:$Vs, HvxVR:$Vt)>; + def: Pat<(VecQ32 (setugt HVI32:$Vs, HVI32:$Vt)), + (V6_vgtuw HvxVR:$Vs, HvxVR:$Vt)>; + def: Pat<(VecI8 (trunc HWI16:$Vss)), (V6_vpackeb (HiVec $Vss), (LoVec $Vss))>; def: Pat<(VecI16 (trunc HWI32:$Vss)), diff --git a/test/CodeGen/Hexagon/autohvx/vector-compare-128b.ll b/test/CodeGen/Hexagon/autohvx/vector-compare-128b.ll index b4d78d5e50f..dd15518dbd8 100644 --- a/test/CodeGen/Hexagon/autohvx/vector-compare-128b.ll +++ b/test/CodeGen/Hexagon/autohvx/vector-compare-128b.ll @@ -13,8 +13,7 @@ define <128 x i8> @test_00(<128 x i8> %v0, <128 x i8> %v1) #0 { ; CHECK-LABEL: test_01: ; CHECK: q[[Q010:[0-3]]] = vcmp.eq(v0.b,v1.b) -; CHECK: q[[Q011:[0-9]]] = not(q[[Q010]]) -; CHECK: v0 = vmux(q[[Q011]],v0,v1) +; CHECK: v0 = vmux(q[[Q010]],v1,v0) define <128 x i8> @test_01(<128 x i8> %v0, <128 x i8> %v1) #0 { %t0 = icmp ne <128 x i8> %v0, %v1 %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1 @@ -32,8 +31,7 @@ define <128 x i8> @test_02(<128 x i8> %v0, <128 x i8> %v1) #0 { ; CHECK-LABEL: test_03: ; CHECK: q[[Q030:[0-3]]] = vcmp.gt(v0.b,v1.b) -; CHECK: q[[Q031:[0-9]]] = not(q[[Q030]]) -; CHECK: v0 = vmux(q[[Q031]],v0,v1) +; CHECK: v0 = vmux(q[[Q030]],v1,v0) define <128 x i8> @test_03(<128 x i8> %v0, <128 x i8> %v1) #0 { %t0 = icmp sle <128 x i8> %v0, %v1 %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1 @@ -51,8 +49,7 @@ define <128 x i8> @test_04(<128 x i8> %v0, <128 x i8> %v1) #0 { ; CHECK-LABEL: test_05: ; CHECK: q[[Q050:[0-3]]] = vcmp.gt(v1.b,v0.b) -; CHECK: q[[Q051:[0-9]]] = not(q[[Q050]]) -; CHECK: v0 = vmux(q[[Q051]],v0,v1) +; CHECK: v0 = vmux(q[[Q050]],v1,v0) define <128 x i8> @test_05(<128 x i8> %v0, <128 x i8> %v1) #0 { %t0 = icmp sge <128 x i8> %v0, %v1 %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1 @@ -70,8 +67,7 @@ define <128 x i8> @test_06(<128 x i8> %v0, <128 x i8> %v1) #0 { ; CHECK-LABEL: test_07: ; CHECK: q[[Q070:[0-3]]] = vcmp.gt(v0.ub,v1.ub) -; CHECK: q[[Q071:[0-9]]] = not(q[[Q070]]) -; CHECK: v0 = vmux(q[[Q071]],v0,v1) +; CHECK: v0 = vmux(q[[Q070]],v1,v0) define <128 x i8> @test_07(<128 x i8> %v0, <128 x i8> %v1) #0 { %t0 = icmp ule <128 x i8> %v0, %v1 %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1 @@ -89,8 +85,7 @@ define <128 x i8> @test_08(<128 x i8> %v0, <128 x i8> %v1) #0 { ; CHECK-LABEL: test_09: ; CHECK: q[[Q090:[0-3]]] = vcmp.gt(v1.ub,v0.ub) -; CHECK: q[[Q091:[0-9]]] = not(q[[Q090]]) -; CHECK: v0 = vmux(q[[Q091]],v0,v1) +; CHECK: v0 = vmux(q[[Q090]],v1,v0) define <128 x i8> @test_09(<128 x i8> %v0, <128 x i8> %v1) #0 { %t0 = icmp uge <128 x i8> %v0, %v1 %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1 @@ -110,8 +105,7 @@ define <64 x i16> @test_10(<64 x i16> %v0, <64 x i16> %v1) #0 { ; CHECK-LABEL: test_11: ; CHECK: q[[Q110:[0-3]]] = vcmp.eq(v0.h,v1.h) -; CHECK: q[[Q111:[0-9]]] = not(q[[Q110]]) -; CHECK: v0 = vmux(q[[Q111]],v0,v1) +; CHECK: v0 = vmux(q[[Q110]],v1,v0) define <64 x i16> @test_11(<64 x i16> %v0, <64 x i16> %v1) #0 { %t0 = icmp ne <64 x i16> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1 @@ -129,8 +123,7 @@ define <64 x i16> @test_12(<64 x i16> %v0, <64 x i16> %v1) #0 { ; CHECK-LABEL: test_13: ; CHECK: q[[Q130:[0-3]]] = vcmp.gt(v0.h,v1.h) -; CHECK: q[[Q131:[0-9]]] = not(q[[Q130]]) -; CHECK: v0 = vmux(q[[Q031]],v0,v1) +; CHECK: v0 = vmux(q[[Q130]],v1,v0) define <64 x i16> @test_13(<64 x i16> %v0, <64 x i16> %v1) #0 { %t0 = icmp sle <64 x i16> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1 @@ -148,8 +141,7 @@ define <64 x i16> @test_14(<64 x i16> %v0, <64 x i16> %v1) #0 { ; CHECK-LABEL: test_15: ; CHECK: q[[Q150:[0-3]]] = vcmp.gt(v1.h,v0.h) -; CHECK: q[[Q151:[0-9]]] = not(q[[Q150]]) -; CHECK: v0 = vmux(q[[Q151]],v0,v1) +; CHECK: v0 = vmux(q[[Q150]],v1,v0) define <64 x i16> @test_15(<64 x i16> %v0, <64 x i16> %v1) #0 { %t0 = icmp sge <64 x i16> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1 @@ -167,8 +159,7 @@ define <64 x i16> @test_16(<64 x i16> %v0, <64 x i16> %v1) #0 { ; CHECK-LABEL: test_17: ; CHECK: q[[Q170:[0-3]]] = vcmp.gt(v0.uh,v1.uh) -; CHECK: q[[Q171:[0-9]]] = not(q[[Q170]]) -; CHECK: v0 = vmux(q[[Q171]],v0,v1) +; CHECK: v0 = vmux(q[[Q170]],v1,v0) define <64 x i16> @test_17(<64 x i16> %v0, <64 x i16> %v1) #0 { %t0 = icmp ule <64 x i16> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1 @@ -186,8 +177,7 @@ define <64 x i16> @test_18(<64 x i16> %v0, <64 x i16> %v1) #0 { ; CHECK-LABEL: test_19: ; CHECK: q[[Q190:[0-3]]] = vcmp.gt(v1.uh,v0.uh) -; CHECK: q[[Q191:[0-9]]] = not(q[[Q190]]) -; CHECK: v0 = vmux(q[[Q191]],v0,v1) +; CHECK: v0 = vmux(q[[Q190]],v1,v0) define <64 x i16> @test_19(<64 x i16> %v0, <64 x i16> %v1) #0 { %t0 = icmp uge <64 x i16> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1 @@ -207,8 +197,7 @@ define <32 x i32> @test_20(<32 x i32> %v0, <32 x i32> %v1) #0 { ; CHECK-LABEL: test_21: ; CHECK: q[[Q210:[0-3]]] = vcmp.eq(v0.w,v1.w) -; CHECK: q[[Q211:[0-9]]] = not(q[[Q210]]) -; CHECK: v0 = vmux(q[[Q211]],v0,v1) +; CHECK: v0 = vmux(q[[Q210]],v1,v0) define <32 x i32> @test_21(<32 x i32> %v0, <32 x i32> %v1) #0 { %t0 = icmp ne <32 x i32> %v0, %v1 %t1 = select <32 x i1> %t0, <32 x i32> %v0, <32 x i32> %v1 @@ -226,8 +215,7 @@ define <32 x i32> @test_22(<32 x i32> %v0, <32 x i32> %v1) #0 { ; CHECK-LABEL: test_23: ; CHECK: q[[Q230:[0-3]]] = vcmp.gt(v0.w,v1.w) -; CHECK: q[[Q231:[0-9]]] = not(q[[Q230]]) -; CHECK: v0 = vmux(q[[Q031]],v0,v1) +; CHECK: v0 = vmux(q[[Q230]],v1,v0) define <32 x i32> @test_23(<32 x i32> %v0, <32 x i32> %v1) #0 { %t0 = icmp sle <32 x i32> %v0, %v1 %t1 = select <32 x i1> %t0, <32 x i32> %v0, <32 x i32> %v1 @@ -245,8 +233,7 @@ define <32 x i32> @test_24(<32 x i32> %v0, <32 x i32> %v1) #0 { ; CHECK-LABEL: test_25: ; CHECK: q[[Q250:[0-3]]] = vcmp.gt(v1.w,v0.w) -; CHECK: q[[Q251:[0-9]]] = not(q[[Q250]]) -; CHECK: v0 = vmux(q[[Q251]],v0,v1) +; CHECK: v0 = vmux(q[[Q250]],v1,v0) define <32 x i32> @test_25(<32 x i32> %v0, <32 x i32> %v1) #0 { %t0 = icmp sge <32 x i32> %v0, %v1 %t1 = select <32 x i1> %t0, <32 x i32> %v0, <32 x i32> %v1 @@ -264,8 +251,7 @@ define <32 x i32> @test_26(<32 x i32> %v0, <32 x i32> %v1) #0 { ; CHECK-LABEL: test_27: ; CHECK: q[[Q270:[0-3]]] = vcmp.gt(v0.uw,v1.uw) -; CHECK: q[[Q271:[0-9]]] = not(q[[Q270]]) -; CHECK: v0 = vmux(q[[Q271]],v0,v1) +; CHECK: v0 = vmux(q[[Q270]],v1,v0) define <32 x i32> @test_27(<32 x i32> %v0, <32 x i32> %v1) #0 { %t0 = icmp ule <32 x i32> %v0, %v1 %t1 = select <32 x i1> %t0, <32 x i32> %v0, <32 x i32> %v1 @@ -283,8 +269,7 @@ define <32 x i32> @test_28(<32 x i32> %v0, <32 x i32> %v1) #0 { ; CHECK-LABEL: test_29: ; CHECK: q[[Q290:[0-3]]] = vcmp.gt(v1.uw,v0.uw) -; CHECK: q[[Q291:[0-9]]] = not(q[[Q290]]) -; CHECK: v0 = vmux(q[[Q291]],v0,v1) +; CHECK: v0 = vmux(q[[Q290]],v1,v0) define <32 x i32> @test_29(<32 x i32> %v0, <32 x i32> %v1) #0 { %t0 = icmp uge <32 x i32> %v0, %v1 %t1 = select <32 x i1> %t0, <32 x i32> %v0, <32 x i32> %v1 diff --git a/test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll b/test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll index 4c0e19791d4..39a117f4ecd 100644 --- a/test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll +++ b/test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll @@ -13,8 +13,7 @@ define <64 x i8> @test_00(<64 x i8> %v0, <64 x i8> %v1) #0 { ; CHECK-LABEL: test_01: ; CHECK: q[[Q010:[0-3]]] = vcmp.eq(v0.b,v1.b) -; CHECK: q[[Q011:[0-9]]] = not(q[[Q010]]) -; CHECK: v0 = vmux(q[[Q011]],v0,v1) +; CHECK: v0 = vmux(q[[Q010]],v1,v0) define <64 x i8> @test_01(<64 x i8> %v0, <64 x i8> %v1) #0 { %t0 = icmp ne <64 x i8> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1 @@ -32,8 +31,7 @@ define <64 x i8> @test_02(<64 x i8> %v0, <64 x i8> %v1) #0 { ; CHECK-LABEL: test_03: ; CHECK: q[[Q030:[0-3]]] = vcmp.gt(v0.b,v1.b) -; CHECK: q[[Q031:[0-9]]] = not(q[[Q030]]) -; CHECK: v0 = vmux(q[[Q031]],v0,v1) +; CHECK: v0 = vmux(q[[Q030]],v1,v0) define <64 x i8> @test_03(<64 x i8> %v0, <64 x i8> %v1) #0 { %t0 = icmp sle <64 x i8> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1 @@ -51,8 +49,7 @@ define <64 x i8> @test_04(<64 x i8> %v0, <64 x i8> %v1) #0 { ; CHECK-LABEL: test_05: ; CHECK: q[[Q050:[0-3]]] = vcmp.gt(v1.b,v0.b) -; CHECK: q[[Q051:[0-9]]] = not(q[[Q050]]) -; CHECK: v0 = vmux(q[[Q051]],v0,v1) +; CHECK: v0 = vmux(q[[Q050]],v1,v0) define <64 x i8> @test_05(<64 x i8> %v0, <64 x i8> %v1) #0 { %t0 = icmp sge <64 x i8> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1 @@ -70,8 +67,7 @@ define <64 x i8> @test_06(<64 x i8> %v0, <64 x i8> %v1) #0 { ; CHECK-LABEL: test_07: ; CHECK: q[[Q070:[0-3]]] = vcmp.gt(v0.ub,v1.ub) -; CHECK: q[[Q071:[0-9]]] = not(q[[Q070]]) -; CHECK: v0 = vmux(q[[Q071]],v0,v1) +; CHECK: v0 = vmux(q[[Q070]],v1,v0) define <64 x i8> @test_07(<64 x i8> %v0, <64 x i8> %v1) #0 { %t0 = icmp ule <64 x i8> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1 @@ -89,8 +85,7 @@ define <64 x i8> @test_08(<64 x i8> %v0, <64 x i8> %v1) #0 { ; CHECK-LABEL: test_09: ; CHECK: q[[Q090:[0-3]]] = vcmp.gt(v1.ub,v0.ub) -; CHECK: q[[Q091:[0-9]]] = not(q[[Q090]]) -; CHECK: v0 = vmux(q[[Q091]],v0,v1) +; CHECK: v0 = vmux(q[[Q090]],v1,v0) define <64 x i8> @test_09(<64 x i8> %v0, <64 x i8> %v1) #0 { %t0 = icmp uge <64 x i8> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1 @@ -110,8 +105,7 @@ define <32 x i16> @test_10(<32 x i16> %v0, <32 x i16> %v1) #0 { ; CHECK-LABEL: test_11: ; CHECK: q[[Q110:[0-3]]] = vcmp.eq(v0.h,v1.h) -; CHECK: q[[Q111:[0-9]]] = not(q[[Q110]]) -; CHECK: v0 = vmux(q[[Q111]],v0,v1) +; CHECK: v0 = vmux(q[[Q110]],v1,v0) define <32 x i16> @test_11(<32 x i16> %v0, <32 x i16> %v1) #0 { %t0 = icmp ne <32 x i16> %v0, %v1 %t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1 @@ -129,8 +123,7 @@ define <32 x i16> @test_12(<32 x i16> %v0, <32 x i16> %v1) #0 { ; CHECK-LABEL: test_13: ; CHECK: q[[Q130:[0-3]]] = vcmp.gt(v0.h,v1.h) -; CHECK: q[[Q131:[0-9]]] = not(q[[Q130]]) -; CHECK: v0 = vmux(q[[Q031]],v0,v1) +; CHECK: v0 = vmux(q[[Q130]],v1,v0) define <32 x i16> @test_13(<32 x i16> %v0, <32 x i16> %v1) #0 { %t0 = icmp sle <32 x i16> %v0, %v1 %t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1 @@ -148,8 +141,7 @@ define <32 x i16> @test_14(<32 x i16> %v0, <32 x i16> %v1) #0 { ; CHECK-LABEL: test_15: ; CHECK: q[[Q150:[0-3]]] = vcmp.gt(v1.h,v0.h) -; CHECK: q[[Q151:[0-9]]] = not(q[[Q150]]) -; CHECK: v0 = vmux(q[[Q151]],v0,v1) +; CHECK: v0 = vmux(q[[Q150]],v1,v0) define <32 x i16> @test_15(<32 x i16> %v0, <32 x i16> %v1) #0 { %t0 = icmp sge <32 x i16> %v0, %v1 %t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1 @@ -167,8 +159,7 @@ define <32 x i16> @test_16(<32 x i16> %v0, <32 x i16> %v1) #0 { ; CHECK-LABEL: test_17: ; CHECK: q[[Q170:[0-3]]] = vcmp.gt(v0.uh,v1.uh) -; CHECK: q[[Q171:[0-9]]] = not(q[[Q170]]) -; CHECK: v0 = vmux(q[[Q171]],v0,v1) +; CHECK: v0 = vmux(q[[Q170]],v1,v0) define <32 x i16> @test_17(<32 x i16> %v0, <32 x i16> %v1) #0 { %t0 = icmp ule <32 x i16> %v0, %v1 %t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1 @@ -186,8 +177,7 @@ define <32 x i16> @test_18(<32 x i16> %v0, <32 x i16> %v1) #0 { ; CHECK-LABEL: test_19: ; CHECK: q[[Q190:[0-3]]] = vcmp.gt(v1.uh,v0.uh) -; CHECK: q[[Q191:[0-9]]] = not(q[[Q190]]) -; CHECK: v0 = vmux(q[[Q191]],v0,v1) +; CHECK: v0 = vmux(q[[Q190]],v1,v0) define <32 x i16> @test_19(<32 x i16> %v0, <32 x i16> %v1) #0 { %t0 = icmp uge <32 x i16> %v0, %v1 %t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1 @@ -207,8 +197,7 @@ define <16 x i32> @test_20(<16 x i32> %v0, <16 x i32> %v1) #0 { ; CHECK-LABEL: test_21: ; CHECK: q[[Q210:[0-3]]] = vcmp.eq(v0.w,v1.w) -; CHECK: q[[Q211:[0-9]]] = not(q[[Q210]]) -; CHECK: v0 = vmux(q[[Q211]],v0,v1) +; CHECK: v0 = vmux(q[[Q210]],v1,v0) define <16 x i32> @test_21(<16 x i32> %v0, <16 x i32> %v1) #0 { %t0 = icmp ne <16 x i32> %v0, %v1 %t1 = select <16 x i1> %t0, <16 x i32> %v0, <16 x i32> %v1 @@ -226,8 +215,7 @@ define <16 x i32> @test_22(<16 x i32> %v0, <16 x i32> %v1) #0 { ; CHECK-LABEL: test_23: ; CHECK: q[[Q230:[0-3]]] = vcmp.gt(v0.w,v1.w) -; CHECK: q[[Q231:[0-9]]] = not(q[[Q230]]) -; CHECK: v0 = vmux(q[[Q031]],v0,v1) +; CHECK: v0 = vmux(q[[Q230]],v1,v0) define <16 x i32> @test_23(<16 x i32> %v0, <16 x i32> %v1) #0 { %t0 = icmp sle <16 x i32> %v0, %v1 %t1 = select <16 x i1> %t0, <16 x i32> %v0, <16 x i32> %v1 @@ -245,8 +233,7 @@ define <16 x i32> @test_24(<16 x i32> %v0, <16 x i32> %v1) #0 { ; CHECK-LABEL: test_25: ; CHECK: q[[Q250:[0-3]]] = vcmp.gt(v1.w,v0.w) -; CHECK: q[[Q251:[0-9]]] = not(q[[Q250]]) -; CHECK: v0 = vmux(q[[Q251]],v0,v1) +; CHECK: v0 = vmux(q[[Q250]],v1,v0) define <16 x i32> @test_25(<16 x i32> %v0, <16 x i32> %v1) #0 { %t0 = icmp sge <16 x i32> %v0, %v1 %t1 = select <16 x i1> %t0, <16 x i32> %v0, <16 x i32> %v1 @@ -264,8 +251,7 @@ define <16 x i32> @test_26(<16 x i32> %v0, <16 x i32> %v1) #0 { ; CHECK-LABEL: test_27: ; CHECK: q[[Q270:[0-3]]] = vcmp.gt(v0.uw,v1.uw) -; CHECK: q[[Q271:[0-9]]] = not(q[[Q270]]) -; CHECK: v0 = vmux(q[[Q271]],v0,v1) +; CHECK: v0 = vmux(q[[Q270]],v1,v0) define <16 x i32> @test_27(<16 x i32> %v0, <16 x i32> %v1) #0 { %t0 = icmp ule <16 x i32> %v0, %v1 %t1 = select <16 x i1> %t0, <16 x i32> %v0, <16 x i32> %v1 @@ -283,8 +269,7 @@ define <16 x i32> @test_28(<16 x i32> %v0, <16 x i32> %v1) #0 { ; CHECK-LABEL: test_29: ; CHECK: q[[Q290:[0-3]]] = vcmp.gt(v1.uw,v0.uw) -; CHECK: q[[Q291:[0-9]]] = not(q[[Q290]]) -; CHECK: v0 = vmux(q[[Q291]],v0,v1) +; CHECK: v0 = vmux(q[[Q290]],v1,v0) define <16 x i32> @test_29(<16 x i32> %v0, <16 x i32> %v1) #0 { %t0 = icmp uge <16 x i32> %v0, %v1 %t1 = select <16 x i1> %t0, <16 x i32> %v0, <16 x i32> %v1