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Move PPCFrameLowering into PPCSubtarget from PPCTargetMachine. Use

Browse Source 
the initializeSubtargetDependencies code to obtain an initialized
subtarget and migrate a couple of subtarget using functions to the
.cpp file to avoid circular includes.

llvm-svn: 210822
This commit is contained in:
Eric Christopher 2014-06-12 20:54:11 +00:00
parent 97517d926c
commit 0c6467adf3
6 changed files with 211 additions and 196 deletions
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186
lib/Target/PowerPC/PPCFrameLowering.cpp
View File

@ -15,6 +15,7 @@
#include "PPCInstrBuilder.h"
#include "PPCInstrInfo.h"
#include "PPCMachineFunctionInfo.h"
#include "PPCSubtarget.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
@ -35,6 +36,191 @@ static const uint16_t VRRegNo[] = {
PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
};
PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI)
: TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
(STI.hasQPX() || STI.isBGQ()) ? 32 : 16, 0),
Subtarget(STI) {}
unsigned PPCFrameLowering::getMinCallArgumentsSize(bool isPPC64,
bool isDarwinABI) {
// For the Darwin ABI / 64-bit SVR4 ABI:
// The prolog code of the callee may store up to 8 GPR argument registers to
// the stack, allowing va_start to index over them in memory if its varargs.
// Because we cannot tell if this is needed on the caller side, we have to
// conservatively assume that it is needed. As such, make sure we have at
// least enough stack space for the caller to store the 8 GPRs.
if (isDarwinABI || isPPC64)
return 8 * (isPPC64 ? 8 : 4);
// 32-bit SVR4 ABI:
// There is no default stack allocated for the 8 first GPR arguments.
return 0;
}
/// getMinCallFrameSize - Return the minimum size a call frame can be using
/// the PowerPC ABI.
unsigned PPCFrameLowering::getMinCallFrameSize(bool isPPC64, bool isDarwinABI) {
// The call frame needs to be at least big enough for linkage and 8 args.
return PPCFrameLowering::getLinkageSize(isPPC64, isDarwinABI) +
PPCFrameLowering::getMinCallArgumentsSize(isPPC64, isDarwinABI);
}
// With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots(
unsigned &NumEntries) const {
if (Subtarget.isDarwinABI()) {
NumEntries = 1;
if (Subtarget.isPPC64()) {
static const SpillSlot darwin64Offsets = {PPC::X31, -8};
return &darwin64Offsets;
} else {
static const SpillSlot darwinOffsets = {PPC::R31, -4};
return &darwinOffsets;
}
}
// Early exit if not using the SVR4 ABI.
if (!Subtarget.isSVR4ABI()) {
NumEntries = 0;
return nullptr;
}
// Note that the offsets here overlap, but this is fixed up in
// processFunctionBeforeFrameFinalized.
static const SpillSlot Offsets[] = {
// Floating-point register save area offsets.
{PPC::F31, -8},
{PPC::F30, -16},
{PPC::F29, -24},
{PPC::F28, -32},
{PPC::F27, -40},
{PPC::F26, -48},
{PPC::F25, -56},
{PPC::F24, -64},
{PPC::F23, -72},
{PPC::F22, -80},
{PPC::F21, -88},
{PPC::F20, -96},
{PPC::F19, -104},
{PPC::F18, -112},
{PPC::F17, -120},
{PPC::F16, -128},
{PPC::F15, -136},
{PPC::F14, -144},
// General register save area offsets.
{PPC::R31, -4},
{PPC::R30, -8},
{PPC::R29, -12},
{PPC::R28, -16},
{PPC::R27, -20},
{PPC::R26, -24},
{PPC::R25, -28},
{PPC::R24, -32},
{PPC::R23, -36},
{PPC::R22, -40},
{PPC::R21, -44},
{PPC::R20, -48},
{PPC::R19, -52},
{PPC::R18, -56},
{PPC::R17, -60},
{PPC::R16, -64},
{PPC::R15, -68},
{PPC::R14, -72},
// CR save area offset. We map each of the nonvolatile CR fields
// to the slot for CR2, which is the first of the nonvolatile CR
// fields to be assigned, so that we only allocate one save slot.
// See PPCRegisterInfo::hasReservedSpillSlot() for more information.
{PPC::CR2, -4},
// VRSAVE save area offset.
{PPC::VRSAVE, -4},
// Vector register save area
{PPC::V31, -16},
{PPC::V30, -32},
{PPC::V29, -48},
{PPC::V28, -64},
{PPC::V27, -80},
{PPC::V26, -96},
{PPC::V25, -112},
{PPC::V24, -128},
{PPC::V23, -144},
{PPC::V22, -160},
{PPC::V21, -176},
{PPC::V20, -192}};
static const SpillSlot Offsets64[] = {
// Floating-point register save area offsets.
{PPC::F31, -8},
{PPC::F30, -16},
{PPC::F29, -24},
{PPC::F28, -32},
{PPC::F27, -40},
{PPC::F26, -48},
{PPC::F25, -56},
{PPC::F24, -64},
{PPC::F23, -72},
{PPC::F22, -80},
{PPC::F21, -88},
{PPC::F20, -96},
{PPC::F19, -104},
{PPC::F18, -112},
{PPC::F17, -120},
{PPC::F16, -128},
{PPC::F15, -136},
{PPC::F14, -144},
// General register save area offsets.
{PPC::X31, -8},
{PPC::X30, -16},
{PPC::X29, -24},
{PPC::X28, -32},
{PPC::X27, -40},
{PPC::X26, -48},
{PPC::X25, -56},
{PPC::X24, -64},
{PPC::X23, -72},
{PPC::X22, -80},
{PPC::X21, -88},
{PPC::X20, -96},
{PPC::X19, -104},
{PPC::X18, -112},
{PPC::X17, -120},
{PPC::X16, -128},
{PPC::X15, -136},
{PPC::X14, -144},
// VRSAVE save area offset.
{PPC::VRSAVE, -4},
// Vector register save area
{PPC::V31, -16},
{PPC::V30, -32},
{PPC::V29, -48},
{PPC::V28, -64},
{PPC::V27, -80},
{PPC::V26, -96},
{PPC::V25, -112},
{PPC::V24, -128},
{PPC::V23, -144},
{PPC::V22, -160},
{PPC::V21, -176},
{PPC::V20, -192}};
if (Subtarget.isPPC64()) {
NumEntries = array_lengthof(Offsets64);
return Offsets64;
} else {
NumEntries = array_lengthof(Offsets);
return Offsets;
}
}
/// RemoveVRSaveCode - We have found that this function does not need any code
/// to manipulate the VRSAVE register, even though it uses vector registers.
/// This can happen when the only registers used are known to be live in or out

192
lib/Target/PowerPC/PPCFrameLowering.h
View File

@ -14,23 +14,18 @@
#define POWERPC_FRAMEINFO_H
#include "PPC.h"
#include "PPCSubtarget.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
class PPCSubtarget;
class PPCSubtarget;
class PPCFrameLowering: public TargetFrameLowering {
const PPCSubtarget &Subtarget;
public:
PPCFrameLowering(const PPCSubtarget &sti)
: TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
(sti.hasQPX() || sti.isBGQ()) ? 32 : 16, 0),
Subtarget(sti) {
}
PPCFrameLowering(const PPCSubtarget &STI);
unsigned determineFrameLayout(MachineFunction &MF,
bool UpdateMF = true,
@ -116,188 +111,11 @@ public:
/// getMinCallArgumentsSize - Return the size of the minium PowerPC ABI
/// argument area.
static unsigned getMinCallArgumentsSize(bool isPPC64, bool isDarwinABI) {
// For the Darwin ABI / 64-bit SVR4 ABI:
// The prolog code of the callee may store up to 8 GPR argument registers to
// the stack, allowing va_start to index over them in memory if its varargs.
// Because we cannot tell if this is needed on the caller side, we have to
// conservatively assume that it is needed. As such, make sure we have at
// least enough stack space for the caller to store the 8 GPRs.
if (isDarwinABI || isPPC64)
return 8 * (isPPC64 ? 8 : 4);
// 32-bit SVR4 ABI:
// There is no default stack allocated for the 8 first GPR arguments.
return 0;
}
/// getMinCallFrameSize - Return the minimum size a call frame can be using
/// the PowerPC ABI.
static unsigned getMinCallFrameSize(bool isPPC64, bool isDarwinABI) {
// The call frame needs to be at least big enough for linkage and 8 args.
return getLinkageSize(isPPC64, isDarwinABI) +
getMinCallArgumentsSize(isPPC64, isDarwinABI);
}
// With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
static unsigned getMinCallArgumentsSize(bool isPPC64, bool isDarwinABI);
const SpillSlot *
getCalleeSavedSpillSlots(unsigned &NumEntries) const override {
if (Subtarget.isDarwinABI()) {
NumEntries = 1;
if (Subtarget.isPPC64()) {
static const SpillSlot darwin64Offsets = {PPC::X31, -8};
return &darwin64Offsets;
} else {
static const SpillSlot darwinOffsets = {PPC::R31, -4};
return &darwinOffsets;
}
}
// Early exit if not using the SVR4 ABI.
if (!Subtarget.isSVR4ABI()) {
NumEntries = 0;
return nullptr;
}
// Note that the offsets here overlap, but this is fixed up in
// processFunctionBeforeFrameFinalized.
static const SpillSlot Offsets[] = {
// Floating-point register save area offsets.
{PPC::F31, -8},
{PPC::F30, -16},
{PPC::F29, -24},
{PPC::F28, -32},
{PPC::F27, -40},
{PPC::F26, -48},
{PPC::F25, -56},
{PPC::F24, -64},
{PPC::F23, -72},
{PPC::F22, -80},
{PPC::F21, -88},
{PPC::F20, -96},
{PPC::F19, -104},
{PPC::F18, -112},
{PPC::F17, -120},
{PPC::F16, -128},
{PPC::F15, -136},
{PPC::F14, -144},
// General register save area offsets.
{PPC::R31, -4},
{PPC::R30, -8},
{PPC::R29, -12},
{PPC::R28, -16},
{PPC::R27, -20},
{PPC::R26, -24},
{PPC::R25, -28},
{PPC::R24, -32},
{PPC::R23, -36},
{PPC::R22, -40},
{PPC::R21, -44},
{PPC::R20, -48},
{PPC::R19, -52},
{PPC::R18, -56},
{PPC::R17, -60},
{PPC::R16, -64},
{PPC::R15, -68},
{PPC::R14, -72},
// CR save area offset. We map each of the nonvolatile CR fields
// to the slot for CR2, which is the first of the nonvolatile CR
// fields to be assigned, so that we only allocate one save slot.
// See PPCRegisterInfo::hasReservedSpillSlot() for more information.
{PPC::CR2, -4},
// VRSAVE save area offset.
{PPC::VRSAVE, -4},
// Vector register save area
{PPC::V31, -16},
{PPC::V30, -32},
{PPC::V29, -48},
{PPC::V28, -64},
{PPC::V27, -80},
{PPC::V26, -96},
{PPC::V25, -112},
{PPC::V24, -128},
{PPC::V23, -144},
{PPC::V22, -160},
{PPC::V21, -176},
{PPC::V20, -192}
};
static const SpillSlot Offsets64[] = {
// Floating-point register save area offsets.
{PPC::F31, -8},
{PPC::F30, -16},
{PPC::F29, -24},
{PPC::F28, -32},
{PPC::F27, -40},
{PPC::F26, -48},
{PPC::F25, -56},
{PPC::F24, -64},
{PPC::F23, -72},
{PPC::F22, -80},
{PPC::F21, -88},
{PPC::F20, -96},
{PPC::F19, -104},
{PPC::F18, -112},
{PPC::F17, -120},
{PPC::F16, -128},
{PPC::F15, -136},
{PPC::F14, -144},
// General register save area offsets.
{PPC::X31, -8},
{PPC::X30, -16},
{PPC::X29, -24},
{PPC::X28, -32},
{PPC::X27, -40},
{PPC::X26, -48},
{PPC::X25, -56},
{PPC::X24, -64},
{PPC::X23, -72},
{PPC::X22, -80},
{PPC::X21, -88},
{PPC::X20, -96},
{PPC::X19, -104},
{PPC::X18, -112},
{PPC::X17, -120},
{PPC::X16, -128},
{PPC::X15, -136},
{PPC::X14, -144},
// VRSAVE save area offset.
{PPC::VRSAVE, -4},
// Vector register save area
{PPC::V31, -16},
{PPC::V30, -32},
{PPC::V29, -48},
{PPC::V28, -64},
{PPC::V27, -80},
{PPC::V26, -96},
{PPC::V25, -112},
{PPC::V24, -128},
{PPC::V23, -144},
{PPC::V22, -160},
{PPC::V21, -176},
{PPC::V20, -192}
};
if (Subtarget.isPPC64()) {
NumEntries = array_lengthof(Offsets64);
return Offsets64;
} else {
NumEntries = array_lengthof(Offsets);
return Offsets;
}
}
getCalleeSavedSpillSlots(unsigned &NumEntries) const override;
static unsigned getMinCallFrameSize(bool isPPC64, bool isDarwinABI);
};
} // End llvm namespace
#endif

13
lib/Target/PowerPC/PPCSubtarget.cpp
View File

@ -32,14 +32,19 @@ using namespace llvm;
#define GET_SUBTARGETINFO_CTOR
#include "PPCGenSubtargetInfo.inc"
PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
StringRef FS) {
initializeEnvironment();
resetSubtargetFeatures(CPU, FS);
return *this;
}
PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool is64Bit,
CodeGenOpt::Level OptLevel)
: PPCGenSubtargetInfo(TT, CPU, FS), IsPPC64(is64Bit), TargetTriple(TT),
OptLevel(OptLevel) {
initializeEnvironment();
resetSubtargetFeatures(CPU, FS);
}
OptLevel(OptLevel),
FrameLowering(initializeSubtargetDependencies(CPU, FS)) {}
/// SetJITMode - This is called to inform the subtarget info that we are
/// producing code for the JIT.

8
lib/Target/PowerPC/PPCSubtarget.h
View File

@ -14,6 +14,7 @@
#ifndef POWERPCSUBTARGET_H
#define POWERPCSUBTARGET_H
#include "PPCFrameLowering.h"
#include "llvm/ADT/Triple.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Target/TargetSubtargetInfo.h"
@ -102,6 +103,7 @@ protected:
/// OptLevel - What default optimization level we're emitting code for.
CodeGenOpt::Level OptLevel;
PPCFrameLowering FrameLowering;
public:
/// This constructor initializes the data members to match that
/// of the specified triple.
@ -131,6 +133,12 @@ public:
/// selection.
const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
const PPCFrameLowering *getFrameLowering() const { return &FrameLowering; }
/// initializeSubtargetDependencies - Initializes using a CPU and feature string
/// so that we can use initializer lists for subtarget initialization.
PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
/// \brief Reset the features for the PowerPC target.
void resetSubtargetFeatures(const MachineFunction *MF) override;
private:

3
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -78,8 +78,7 @@ PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
CodeGenOpt::Level OL, bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS, is64Bit, OL), DL(getDataLayoutString(Subtarget)),
InstrInfo(*this), FrameLowering(Subtarget), JITInfo(*this, is64Bit),
TLInfo(*this), TSInfo(*this) {
InstrInfo(*this), JITInfo(*this, is64Bit), TLInfo(*this), TSInfo(*this) {
initAsmInfo();
}

5
lib/Target/PowerPC/PPCTargetMachine.h
View File

@ -31,7 +31,6 @@ class PPCTargetMachine : public LLVMTargetMachine {
PPCSubtarget Subtarget;
const DataLayout DL; // Calculates type size & alignment
PPCInstrInfo InstrInfo;
PPCFrameLowering FrameLowering;
PPCJITInfo JITInfo;
PPCTargetLowering TLInfo;
PPCSelectionDAGInfo TSInfo;
@ -43,8 +42,8 @@ public:
CodeGenOpt::Level OL, bool is64Bit);
const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
const PPCFrameLowering *getFrameLowering() const override {
return &FrameLowering;
const PPCFrameLowering *getFrameLowering() const override {
return getSubtargetImpl()->getFrameLowering();
}
PPCJITInfo *getJITInfo() override { return &JITInfo; }
const PPCTargetLowering *getTargetLowering() const override {