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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 02:52:53 +02:00

Fix lint assert on integer vector division

llvm-svn: 189290
This commit is contained in:
Matt Arsenault 2013-08-26 23:29:33 +00:00
parent 04da79d6a3
commit 0c955e9568
3 changed files with 113 additions and 6 deletions

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@ -504,14 +504,42 @@ void Lint::visitShl(BinaryOperator &I) {
"Undefined result: Shift count out of range", &I);
}
static bool isZero(Value *V, DataLayout *TD) {
static bool isZero(Value *V, DataLayout *DL) {
// Assume undef could be zero.
if (isa<UndefValue>(V)) return true;
if (isa<UndefValue>(V))
return true;
unsigned BitWidth = cast<IntegerType>(V->getType())->getBitWidth();
APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
ComputeMaskedBits(V, KnownZero, KnownOne, TD);
return KnownZero.isAllOnesValue();
VectorType *VecTy = dyn_cast<VectorType>(V->getType());
if (!VecTy) {
unsigned BitWidth = V->getType()->getIntegerBitWidth();
APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
ComputeMaskedBits(V, KnownZero, KnownOne, DL);
return KnownZero.isAllOnesValue();
}
// Per-component check doesn't work with zeroinitializer
Constant *C = dyn_cast<Constant>(V);
if (!C)
return false;
if (C->isZeroValue())
return true;
// For a vector, KnownZero will only be true if all values are zero, so check
// this per component
unsigned BitWidth = VecTy->getElementType()->getIntegerBitWidth();
for (unsigned I = 0, N = VecTy->getNumElements(); I != N; ++I) {
Constant *Elem = C->getAggregateElement(I);
if (isa<UndefValue>(Elem))
return true;
APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
ComputeMaskedBits(Elem, KnownZero, KnownOne, DL);
if (KnownZero.isAllOnesValue())
return true;
}
return false;
}
void Lint::visitSDiv(BinaryOperator &I) {

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@ -0,0 +1,78 @@
; RUN: opt -lint -disable-output %s 2>&1 | FileCheck %s
define <2 x i32> @use_vector_sdiv(<2 x i32> %a) nounwind {
%b = sdiv <2 x i32> %a, <i32 5, i32 8>
ret <2 x i32> %b
}
define <2 x i32> @use_vector_srem(<2 x i32> %a) nounwind {
%b = srem <2 x i32> %a, <i32 5, i32 8>
ret <2 x i32> %b
}
define <2 x i32> @use_vector_udiv(<2 x i32> %a) nounwind {
%b = udiv <2 x i32> %a, <i32 5, i32 8>
ret <2 x i32> %b
}
define <2 x i32> @use_vector_urem(<2 x i32> %a) nounwind {
%b = urem <2 x i32> %a, <i32 5, i32 8>
ret <2 x i32> %b
}
define i32 @use_sdiv_by_zero(i32 %a) nounwind {
; CHECK: Undefined behavior: Division by zero
; CHECK-NEXT: %b = sdiv i32 %a, 0
%b = sdiv i32 %a, 0
ret i32 %b
}
define i32 @use_sdiv_by_zeroinitializer(i32 %a) nounwind {
; CHECK: Undefined behavior: Division by zero
; CHECK-NEXT: %b = sdiv i32 %a, 0
%b = sdiv i32 %a, zeroinitializer
ret i32 %b
}
define <2 x i32> @use_vector_sdiv_by_zero_x(<2 x i32> %a) nounwind {
; CHECK: Undefined behavior: Division by zero
; CHECK-NEXT: %b = sdiv <2 x i32> %a, <i32 0, i32 5>
%b = sdiv <2 x i32> %a, <i32 0, i32 5>
ret <2 x i32> %b
}
define <2 x i32> @use_vector_sdiv_by_zero_y(<2 x i32> %a) nounwind {
; CHECK: Undefined behavior: Division by zero
; CHECK-NEXT: %b = sdiv <2 x i32> %a, <i32 4, i32 0>
%b = sdiv <2 x i32> %a, <i32 4, i32 0>
ret <2 x i32> %b
}
define <2 x i32> @use_vector_sdiv_by_zero_xy(<2 x i32> %a) nounwind {
; CHECK: Undefined behavior: Division by zero
; CHECK-NEXT: %b = sdiv <2 x i32> %a, zeroinitializer
%b = sdiv <2 x i32> %a, <i32 0, i32 0>
ret <2 x i32> %b
}
define <2 x i32> @use_vector_sdiv_by_undef_x(<2 x i32> %a) nounwind {
; CHECK: Undefined behavior: Division by zero
; CHECK-NEXT: %b = sdiv <2 x i32> %a, <i32 undef, i32 5>
%b = sdiv <2 x i32> %a, <i32 undef, i32 5>
ret <2 x i32> %b
}
define <2 x i32> @use_vector_sdiv_by_undef_y(<2 x i32> %a) nounwind {
; CHECK: Undefined behavior: Division by zero
; CHECK-NEXT: %b = sdiv <2 x i32> %a, <i32 5, i32 undef>
%b = sdiv <2 x i32> %a, <i32 5, i32 undef>
ret <2 x i32> %b
}
define <2 x i32> @use_vector_sdiv_by_undef_xy(<2 x i32> %a) nounwind {
; CHECK: Undefined behavior: Division by zero
; CHECK-NEXT: %b = sdiv <2 x i32> %a, undef
%b = sdiv <2 x i32> %a, <i32 undef, i32 undef>
ret <2 x i32> %b
}

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@ -0,0 +1 @@
config.suffixes = ['.ll']