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Add the missing new files from r343654
llvm-svn: 343655
This commit is contained in:
Daniel Sanders
parent
111851a7ec
commit
0cc3eb8f8b
108
lib/Target/AArch64/AArch64PreLegalizerCombiner.cpp
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108
lib/Target/AArch64/AArch64PreLegalizerCombiner.cpp
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@ -0,0 +1,108 @@
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//=== lib/CodeGen/GlobalISel/AArch64PreLegalizerCombiner.cpp --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass does combining of machine instructions at the generic MI level,
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// before the legalizer.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64TargetMachine.h"
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#include "llvm/CodeGen/GlobalISel/Combiner.h"
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#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
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#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
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#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/Support/Debug.h"
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#define DEBUG_TYPE "aarch64-prelegalizer-combiner"
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using namespace llvm;
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using namespace MIPatternMatch;
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namespace {
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class AArch64PreLegalizerCombinerInfo : public CombinerInfo {
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public:
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AArch64PreLegalizerCombinerInfo()
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: CombinerInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
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/*LegalizerInfo*/ nullptr) {}
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virtual bool combine(CombinerChangeObserver &Observer, MachineInstr &MI,
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MachineIRBuilder &B) const override;
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};
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bool AArch64PreLegalizerCombinerInfo::combine(CombinerChangeObserver &Observer,
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MachineInstr &MI,
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MachineIRBuilder &B) const {
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CombinerHelper Helper(Observer, B);
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switch (MI.getOpcode()) {
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default:
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return false;
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case TargetOpcode::G_LOAD:
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case TargetOpcode::G_SEXTLOAD:
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case TargetOpcode::G_ZEXTLOAD:
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return Helper.tryCombineExtendingLoads(MI);
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}
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return false;
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}
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// Pass boilerplate
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// ================
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class AArch64PreLegalizerCombiner : public MachineFunctionPass {
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public:
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static char ID;
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AArch64PreLegalizerCombiner();
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StringRef getPassName() const override { return "AArch64PreLegalizerCombiner"; }
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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};
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}
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void AArch64PreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<TargetPassConfig>();
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AU.setPreservesCFG();
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getSelectionDAGFallbackAnalysisUsage(AU);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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AArch64PreLegalizerCombiner::AArch64PreLegalizerCombiner() : MachineFunctionPass(ID) {
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initializeAArch64PreLegalizerCombinerPass(*PassRegistry::getPassRegistry());
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}
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bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
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if (MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::FailedISel))
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return false;
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auto *TPC = &getAnalysis<TargetPassConfig>();
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AArch64PreLegalizerCombinerInfo PCInfo;
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Combiner C(PCInfo, TPC);
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return C.combineMachineInstrs(MF);
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}
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char AArch64PreLegalizerCombiner::ID = 0;
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INITIALIZE_PASS_BEGIN(AArch64PreLegalizerCombiner, DEBUG_TYPE,
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"Combine AArch64 machine instrs before legalization",
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false, false)
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INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
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INITIALIZE_PASS_END(AArch64PreLegalizerCombiner, DEBUG_TYPE,
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"Combine AArch64 machine instrs before legalization", false,
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false)
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namespace llvm {
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FunctionPass *createAArch64PreLegalizeCombiner() {
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return new AArch64PreLegalizerCombiner();
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}
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} // end namespace llvm
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@ -0,0 +1,450 @@
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# RUN: llc -O0 -run-pass=aarch64-prelegalizer-combiner -global-isel %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--"
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define void @test_anyext(i8* %addr) {
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entry:
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ret void
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}
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define void @test_anyext_with_copy(i8* %addr) {
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entry:
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ret void
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}
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define void @test_signext(i8* %addr) {
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entry:
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ret void
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}
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define void @test_zeroext(i8* %addr) {
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entry:
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ret void
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}
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define void @test_2anyext(i8* %addr) {
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entry:
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ret void
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}
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define void @test_1anyext_1signext(i8* %addr) {
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entry:
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ret void
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}
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define void @test_1xor_1signext(i8* %addr) {
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entry:
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ret void
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}
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define void @test_1anyext_1zeroext(i8* %addr) {
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entry:
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ret void
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}
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define void @test_1signext_1zeroext(i8* %addr) {
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entry:
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ret void
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}
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define void @test_1anyext64_1signext32(i8* %addr) {
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entry:
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ret void
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}
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define void @test_1anyext32_1signext64(i8* %addr) {
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entry:
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ret void
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}
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define void @test_2anyext32_1signext64(i8* %addr) {
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entry:
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ret void
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}
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define void @test_multiblock_anyext(i8* %addr) {
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entry:
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ret void
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}
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define void @test_multiblock_signext(i8* %addr) {
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entry:
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ret void
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}
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define void @test_multiblock_zeroext(i8* %addr) {
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entry:
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ret void
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}
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define void @test_multiblock_2anyext(i8* %addr) {
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entry:
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ret void
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}
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define void @test_multiblock_1anyext64_1signext32(i8* %addr) {
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entry:
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ret void
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}
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define void @test_multiblock_1anyext32_1signext64(i8* %addr) {
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entry:
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ret void
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}
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define void @test_multiblock_2anyext32_1signext64(i8* %addr) {
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entry:
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ret void
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}
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...
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---
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name: test_anyext
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: test_anyext
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; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr)
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; CHECK: $w0 = COPY [[T1]](s32)
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%0:_(p0) = COPY $x0
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%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
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%2:_(s32) = G_ANYEXT %1
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$w0 = COPY %2
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...
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---
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name: test_anyext_with_copy
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: test_anyext
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; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr)
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; CHECK: $w0 = COPY [[T1]](s32)
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%0:_(p0) = COPY $x0
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%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
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%2:_(s8) = COPY %1
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%3:_(s32) = G_ANYEXT %1
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$w0 = COPY %3
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...
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---
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name: test_signext
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: test_signext
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; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
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; CHECK: $w0 = COPY [[T1]](s32)
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%0:_(p0) = COPY $x0
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%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
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%2:_(s32) = G_SEXT %1
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$w0 = COPY %2
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...
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---
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name: test_zeroext
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: test_zeroext
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; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[T1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
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; CHECK: $w0 = COPY [[T1]](s32)
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%0:_(p0) = COPY $x0
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%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
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%2:_(s32) = G_ZEXT %1
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$w0 = COPY %2
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...
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---
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name: test_2anyext
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: test_2anyext
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; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr)
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; CHECK: $w0 = COPY [[T1]](s32)
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; CHECK: $w1 = COPY [[T1]](s32)
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%0:_(p0) = COPY $x0
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%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
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%2:_(s32) = G_ANYEXT %1
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%3:_(s32) = G_ANYEXT %1
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$w0 = COPY %2
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$w1 = COPY %3
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...
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---
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name: test_1anyext_1signext
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: test_1anyext_1signext
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; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
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; CHECK: $w0 = COPY [[T1]](s32)
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; CHECK: $w1 = COPY [[T1]](s32)
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%0:_(p0) = COPY $x0
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%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
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%2:_(s32) = G_ANYEXT %1
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%3:_(s32) = G_SEXT %1
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$w0 = COPY %2
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$w1 = COPY %3
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...
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---
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name: test_1xor_1signext
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: test_1xor_1signext
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; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
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; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
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; CHECK: [[T3:%[0-9]+]]:_(s8) = G_XOR [[T2]], {{%[0-9]+}}
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; CHECK: [[T4:%[0-9]+]]:_(s32) = G_ANYEXT [[T3]]
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; CHECK: $w0 = COPY [[T4]](s32)
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; CHECK: $w1 = COPY [[T1]](s32)
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%0:_(p0) = COPY $x0
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%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
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%2:_(s8) = G_CONSTANT i32 -1
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%3:_(s8) = G_XOR %1, %2
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%5:_(s32) = G_ANYEXT %3
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%6:_(s32) = G_SEXT %1
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$w0 = COPY %5
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$w1 = COPY %6
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...
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---
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name: test_1anyext_1zeroext
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: test_1anyext_1zeroext
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; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[T1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
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; CHECK: $w0 = COPY [[T1]](s32)
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; CHECK: $w1 = COPY [[T1]](s32)
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%0:_(p0) = COPY $x0
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%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
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%2:_(s32) = G_ANYEXT %1
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%3:_(s32) = G_ZEXT %1
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$w0 = COPY %2
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$w1 = COPY %3
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...
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---
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name: test_1signext_1zeroext
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: test_1signext_1zeroext
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; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
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; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
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; CHECK: [[T3:%[0-9]+]]:_(s32) = G_ZEXT [[T2]]
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; CHECK: $w0 = COPY [[T3]](s32)
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; CHECK: $w1 = COPY [[T1]](s32)
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%0:_(p0) = COPY $x0
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%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
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%2:_(s32) = G_ZEXT %1
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%3:_(s32) = G_SEXT %1
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$w0 = COPY %2
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$w1 = COPY %3
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...
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---
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name: test_1anyext64_1signext32
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: test_1anyext64_1signext32
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; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
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; CHECK: [[T2:%[0-9]+]]:_(s64) = G_ANYEXT [[T1]]
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; CHECK: $x0 = COPY [[T2]](s64)
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; CHECK: $w1 = COPY [[T1]](s32)
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%0:_(p0) = COPY $x0
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%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
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%2:_(s64) = G_ANYEXT %1
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%3:_(s32) = G_SEXT %1
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$x0 = COPY %2
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$w1 = COPY %3
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...
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---
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name: test_1anyext32_1signext64
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: test_1anyext32_1signext64
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; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[T1:%[0-9]+]]:_(s64) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
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; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
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; CHECK: [[T3:%[0-9]+]]:_(s32) = G_ANYEXT [[T2]]
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; CHECK: $w0 = COPY [[T3]](s32)
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; CHECK: $x1 = COPY [[T1]](s64)
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%0:_(p0) = COPY $x0
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%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
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%2:_(s32) = G_ANYEXT %1
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%3:_(s64) = G_SEXT %1
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$w0 = COPY %2
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$x1 = COPY %3
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...
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---
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name: test_2anyext32_1signext64
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: test_2anyext32_1signext64
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; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[T1:%[0-9]+]]:_(s64) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
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; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
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; CHECK: [[T3:%[0-9]+]]:_(s32) = G_ANYEXT [[T2]]
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; CHECK: [[T4:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
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; CHECK: [[T5:%[0-9]+]]:_(s32) = G_ANYEXT [[T4]]
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; CHECK: $w0 = COPY [[T3]](s32)
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; CHECK: $x1 = COPY [[T1]](s64)
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; CHECK: $w2 = COPY [[T5]](s32)
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%0:_(p0) = COPY $x0
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%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
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%2:_(s32) = G_ANYEXT %1
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%3:_(s64) = G_SEXT %1
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%4:_(s32) = G_ANYEXT %1
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$w0 = COPY %2
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$x1 = COPY %3
|
||||
$w2 = COPY %4
|
||||
...
|
||||
|
||||
---
|
||||
name: test_multiblock_anyext
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $x0
|
||||
; CHECK-LABEL: name: test_multiblock_anyext
|
||||
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
|
||||
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr)
|
||||
; CHECK: G_BR %bb.1
|
||||
; CHECK: $w0 = COPY [[T1]](s32)
|
||||
%0:_(p0) = COPY $x0
|
||||
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
|
||||
G_BR %bb.1
|
||||
bb.1:
|
||||
%2:_(s32) = G_ANYEXT %1
|
||||
$w0 = COPY %2
|
||||
...
|
||||
|
||||
---
|
||||
name: test_multiblock_signext
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $x0
|
||||
; CHECK-LABEL: name: test_multiblock_signext
|
||||
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
|
||||
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
|
||||
; CHECK: $w0 = COPY [[T1]](s32)
|
||||
%0:_(p0) = COPY $x0
|
||||
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
|
||||
G_BR %bb.1
|
||||
bb.1:
|
||||
%2:_(s32) = G_SEXT %1
|
||||
$w0 = COPY %2
|
||||
...
|
||||
|
||||
---
|
||||
name: test_multiblock_zeroext
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $x0
|
||||
; CHECK-LABEL: name: test_multiblock_zeroext
|
||||
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
|
||||
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
|
||||
; CHECK: $w0 = COPY [[T1]](s32)
|
||||
%0:_(p0) = COPY $x0
|
||||
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
|
||||
G_BR %bb.1
|
||||
bb.1:
|
||||
%2:_(s32) = G_ZEXT %1
|
||||
$w0 = COPY %2
|
||||
...
|
||||
|
||||
---
|
||||
name: test_multiblock_2anyext
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $x0
|
||||
; CHECK-LABEL: name: test_multiblock
|
||||
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
|
||||
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr)
|
||||
; CHECK: $w0 = COPY [[T1]](s32)
|
||||
; CHECK: $w1 = COPY [[T1]](s32)
|
||||
%0:_(p0) = COPY $x0
|
||||
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
|
||||
%2:_(s32) = G_ANYEXT %1
|
||||
G_BR %bb.1
|
||||
bb.1:
|
||||
%3:_(s32) = G_ANYEXT %1
|
||||
$w0 = COPY %2
|
||||
$w1 = COPY %3
|
||||
...
|
||||
|
||||
---
|
||||
name: test_multiblock_1anyext64_1signext32
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $x0
|
||||
; CHECK-LABEL: name: test_multiblock_1anyext64_1signext32
|
||||
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
|
||||
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
|
||||
; CHECK: G_BR %bb.1
|
||||
; CHECK: [[T2:%[0-9]+]]:_(s64) = G_ANYEXT [[T1]]
|
||||
; CHECK: $x0 = COPY [[T2]](s64)
|
||||
; CHECK: $w1 = COPY [[T1]](s32)
|
||||
%0:_(p0) = COPY $x0
|
||||
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
|
||||
G_BR %bb.1
|
||||
bb.1:
|
||||
%2:_(s64) = G_ANYEXT %1
|
||||
%3:_(s32) = G_SEXT %1
|
||||
$x0 = COPY %2
|
||||
$w1 = COPY %3
|
||||
...
|
||||
|
||||
---
|
||||
name: test_multiblock_1anyext32_1signext64
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $x0
|
||||
; CHECK-LABEL: name: test_multiblock_1anyext32_1signext64
|
||||
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
|
||||
; CHECK: [[T1:%[0-9]+]]:_(s64) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
|
||||
; CHECK: G_BR %bb.1
|
||||
; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
|
||||
; CHECK: [[T3:%[0-9]+]]:_(s32) = G_ANYEXT [[T2]]
|
||||
; CHECK: $w0 = COPY [[T3]](s32)
|
||||
; CHECK: $x1 = COPY [[T1]](s64)
|
||||
%0:_(p0) = COPY $x0
|
||||
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
|
||||
G_BR %bb.1
|
||||
bb.1:
|
||||
%2:_(s32) = G_ANYEXT %1
|
||||
%3:_(s64) = G_SEXT %1
|
||||
$w0 = COPY %2
|
||||
$x1 = COPY %3
|
||||
...
|
||||
|
||||
---
|
||||
name: test_multiblock_2anyext32_1signext64
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $x0
|
||||
; CHECK-LABEL: name: test_multiblock_2anyext32_1signext64
|
||||
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
|
||||
; CHECK: [[T1:%[0-9]+]]:_(s64) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
|
||||
; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
|
||||
; CHECK: [[T3:%[0-9]+]]:_(s32) = G_ANYEXT [[T2]]
|
||||
; CHECK: G_BR %bb.1
|
||||
; CHECK: [[T4:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
|
||||
; CHECK: [[T5:%[0-9]+]]:_(s32) = G_ANYEXT [[T4]]
|
||||
; CHECK: $w0 = COPY [[T5]](s32)
|
||||
; CHECK: $x1 = COPY [[T1]](s64)
|
||||
; CHECK: $w2 = COPY [[T3]](s32)
|
||||
%0:_(p0) = COPY $x0
|
||||
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
|
||||
%4:_(s32) = G_ANYEXT %1
|
||||
G_BR %bb.1
|
||||
bb.1:
|
||||
%2:_(s32) = G_ANYEXT %1
|
||||
%3:_(s64) = G_SEXT %1
|
||||
$w0 = COPY %2
|
||||
$x1 = COPY %3
|
||||
$w2 = COPY %4
|
||||
...
|
||||
|
||||
Loading…
Reference in New Issue
Block a user