RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-20 03:23:01 +02:00
Code Issues Projects Releases Wiki Activity

[ARM] GlobalISel: Support G_SELECT for i32

Browse Source 
* Mark as legal for (s32, i1, s32, s32)
* Map everything into GPRs
* Select to two instructions: a CMP of the condition against 0, to set
  the flags, and a MOVCCr to select between the two inputs based on the
  flags that we've just set

llvm-svn: 306382
This commit is contained in:
Diana Picus 2017-06-27 09:19:51 +00:00
parent af4e296f51
commit 0ccc7d292d
7 changed files with 171 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

50
lib/Target/ARM/ARMInstructionSelector.cpp
View File

@ -46,6 +46,10 @@ private:
MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
const RegisterBankInfo &RBI) const;
bool selectSelect(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII,
MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
const RegisterBankInfo &RBI) const;
const ARMBaseInstrInfo &TII;
const ARMBaseRegisterInfo &TRI;
const ARMBaseTargetMachine &TM;
@ -346,6 +350,50 @@ bool ARMInstructionSelector::selectICmp(MachineInstrBuilder &MIB,
return true;
}
bool ARMInstructionSelector::selectSelect(MachineInstrBuilder &MIB,
const ARMBaseInstrInfo &TII,
MachineRegisterInfo &MRI,
const TargetRegisterInfo &TRI,
const RegisterBankInfo &RBI) const {
auto &MBB = *MIB->getParent();
auto InsertBefore = std::next(MIB->getIterator());
auto &DebugLoc = MIB->getDebugLoc();
// Compare the condition to 0.
auto CondReg = MIB->getOperand(1).getReg();
assert(MRI.getType(CondReg).getSizeInBits() == 1 &&
RBI.getRegBank(CondReg, MRI, TRI)->getID() == ARM::GPRRegBankID &&
"Unsupported types for select operation");
auto CmpI = BuildMI(MBB, InsertBefore, DebugLoc, TII.get(ARM::CMPri))
.addUse(CondReg)
.addImm(0)
.add(predOps(ARMCC::AL));
if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI))
return false;
// Move a value into the result register based on the result of the
// comparison.
auto ResReg = MIB->getOperand(0).getReg();
auto TrueReg = MIB->getOperand(2).getReg();
auto FalseReg = MIB->getOperand(3).getReg();
assert(MRI.getType(ResReg) == MRI.getType(TrueReg) &&
MRI.getType(TrueReg) == MRI.getType(FalseReg) &&
MRI.getType(FalseReg).getSizeInBits() == 32 &&
RBI.getRegBank(TrueReg, MRI, TRI)->getID() == ARM::GPRRegBankID &&
RBI.getRegBank(FalseReg, MRI, TRI)->getID() == ARM::GPRRegBankID &&
"Unsupported types for select operation");
auto Mov1I = BuildMI(MBB, InsertBefore, DebugLoc, TII.get(ARM::MOVCCr))
.addDef(ResReg)
.addUse(TrueReg)
.addUse(FalseReg)
.add(predOps(ARMCC::EQ, ARM::CPSR));
if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI))
return false;
MIB->eraseFromParent();
return true;
}
bool ARMInstructionSelector::select(MachineInstr &I) const {
assert(I.getParent() && "Instruction should be in a basic block!");
assert(I.getParent()->getParent() && "Instruction should be in a function!");
@ -448,6 +496,8 @@ bool ARMInstructionSelector::select(MachineInstr &I) const {
}
case G_ICMP:
return selectICmp(MIB, TII, MRI, TRI, RBI);
case G_SELECT:
return selectSelect(MIB, TII, MRI, TRI, RBI);
case G_GEP:
I.setDesc(TII.get(ARM::ADDrr));
MIB.add(predOps(ARMCC::AL)).add(condCodeOp());

3
lib/Target/ARM/ARMLegalizerInfo.cpp
View File

@ -84,6 +84,9 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
setAction({G_GEP, p0}, Legal);
setAction({G_GEP, 1, s32}, Legal);
setAction({G_SELECT, s32}, Legal);
setAction({G_SELECT, 1, s1}, Legal);
setAction({G_CONSTANT, s32}, Legal);
setAction({G_ICMP, s1}, Legal);

12
lib/Target/ARM/ARMRegisterBankInfo.cpp
View File

@ -255,6 +255,18 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
OperandsMapping =
getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr});
break;
case G_SELECT: {
LLT Ty2 = MRI.getType(MI.getOperand(1).getReg());
(void)Ty2;
assert(Ty.getSizeInBits() == 32 && "Unsupported size for G_SELECT");
assert(Ty2.getSizeInBits() == 1 && "Unsupported size for G_SELECT");
OperandsMapping =
getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
&ARM::ValueMappings[ARM::GPR3OpsIdx],
&ARM::ValueMappings[ARM::GPR3OpsIdx],
&ARM::ValueMappings[ARM::GPR3OpsIdx]});
break;
}
case G_ICMP: {
LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
(void)Ty2;

37
test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
View File

@ -42,6 +42,8 @@
define void @test_constant_imm() { ret void }
define void @test_constant_cimm() { ret void }
define void @test_select() { ret void }
define void @test_soft_fp_double() #0 { ret void }
attributes #0 = { "target-features"="+vfp2,-neonfp" }
@ -1100,6 +1102,41 @@ body: |
BX_RET 14, _, implicit %r0
...
---
name: test_select
# CHECK-LABEL: name: test_select
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: %r0, %r1, %r2
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s1) = COPY %r2
; CHECK: [[VREGC:%[0-9]+]] = COPY %r2
%3(s32) = G_SELECT %2(s1), %0, %1
; CHECK: CMPri [[VREGC]], 0, 14, _, implicit-def %cpsr
; CHECK: [[RES:%[0-9]+]] = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr
%r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[RES]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_soft_fp_double
# CHECK-LABEL: name: test_soft_fp_double
legalized: true

10
test/CodeGen/ARM/GlobalISel/arm-isel.ll
View File

@ -400,3 +400,13 @@ entry:
%r = zext i1 %v to i32
ret i32 %r
}
define arm_aapcscc i32 @test_select_i32(i32 %a, i32 %b, i1 %cond) {
; CHECK-LABEL: test_select_i32
; CHECK: cmp r2, #0
; CHECK: moveq r0, r1
; CHECK: bx lr
entry:
%r = select i1 %cond, i32 %a, i32 %b
ret i32 %r
}

28
test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
View File

@ -39,6 +39,8 @@
define void @test_icmp_s16() { ret void }
define void @test_icmp_s32() { ret void }
define void @test_select_s32() { ret void }
define void @test_fadd_s32() #0 { ret void }
define void @test_fadd_s64() #0 { ret void }
@ -775,6 +777,32 @@ body: |
BX_RET 14, _, implicit %r0
...
---
name: test_select_s32
# CHECK-LABEL: name: test_select_s32
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
body: |
bb.0:
liveins: %r0, %r1, %r2
%0(s32) = COPY %r0
%1(s32) = COPY %r1
%2(s1) = COPY %r2
%3(s32) = G_SELECT %2(s1), %0, %1
; G_SELECT with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}(s32) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}}
%r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0
...
---
name: test_fadd_s32
# CHECK-LABEL: name: test_fadd_s32
legalized: false

31
test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
View File

@ -36,6 +36,8 @@
define void @test_icmp_eq_s32() { ret void }
define void @test_select_s32() { ret void }
define void @test_fadd_s32() #0 { ret void }
define void @test_fadd_s64() #0 { ret void }
@ -739,6 +741,35 @@ body: |
%r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0
...
---
name: test_select_s32
# CHECK-LABEL: name: test_select_s32
legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
# CHECK: - { id: 3, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
body: |
bb.0:
liveins: %r0, %r1, %r2
%0(s32) = COPY %r0
%1(s32) = COPY %r1
%2(s1) = COPY %r2
%3(s32) = G_SELECT %2(s1), %0, %1
%r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0
...
---
name: test_fadd_s32