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[ARM] Update arm-storebytesmerge.ll test. NFC

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This test was using a very odd combination of cortex-m7 and Neon. I have
changed it to thumbv7em only.
This commit is contained in:
David Green 2020-09-11 13:56:57 +01:00
parent b1c94baf31
commit 0d2816ba41
1 changed files with 2 additions and 8 deletions
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10
test/CodeGen/ARM/arm-storebytesmerge.ll
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@ -1,11 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
; RUN: llc -mtriple=thumbv7em-arm-none-eabi %s -o - | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv7em-arm-none-eabi"
; Function Attrs: nounwind
define arm_aapcs_vfpcc void @test(i8* %v50) #0 {
define arm_aapcs_vfpcc void @test(i8* %v50) {
; CHECK-LABEL: test:
; CHECK: @ %bb.0:
; CHECK-NEXT: movw r1, #65534
@ -337,5 +333,3 @@ define arm_aapcs_vfpcc void @test(i8* %v50) #0 {
ret void
}
attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m7" "target-features"="-d32,+dsp,+fp-armv8,+hwdiv,+thumb-mode,-crc,-crypto,-dotprod,-fullfp16,-hwdiv-arm,-neon,-ras" "unsafe-fp-math"="false" "use-soft-float"="false" }