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When the target-independent DAGCombiner inferred a higher alignment for a load,
it would replace the load with one with the higher alignment. However, it did not place the new load in the worklist, which prevented later DAG combines in the same phase (for example, target-specific combines) from ever seeing it. This patch corrects that oversight, and updates some tests whose output changed due to slightly different DAGCombine outputs. llvm-svn: 174343
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@ -7199,12 +7199,15 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) {
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// Try to infer better alignment information than the load already has.
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if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
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if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
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if (Align > LD->getAlignment())
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return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
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if (Align > LD->getAlignment()) {
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SDValue NewLoad =
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DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
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LD->getValueType(0),
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Chain, Ptr, LD->getPointerInfo(),
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LD->getMemoryVT(),
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LD->isVolatile(), LD->isNonTemporal(), Align);
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return CombineTo(N, NewLoad, SDValue(NewLoad.getNode(), 1), true);
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}
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}
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}
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@ -178,7 +178,8 @@ define void @check_i128_stackalign(i32 %val0, i32 %val1, i32 %val2, i32 %val3,
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; Nothing local on stack in current codegen, so first stack is 16 away
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; CHECK: ldr {{x[0-9]+}}, [sp, #16]
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; Important point is that we address sp+24 for second dword
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; CHECK: ldr {{x[0-9]+}}, [sp, #24]
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; CHECK: add [[REG:x[0-9]+]], sp, #16
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; CHECK: ldr {{x[0-9]+}}, {{\[}}[[REG]], #8]
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ret void
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}
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@ -56,9 +56,9 @@ entry:
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%div = sdiv i16 %x, 10
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ret i16 %div
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; CHECK: test6:
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; CHECK: imull $26215, %eax, %eax
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; CHECK: shrl $31, %ecx
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; CHECK: sarl $18, %eax
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; CHECK: imull $26215, %eax, %ecx
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; CHECK: sarl $18, %ecx
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; CHECK: shrl $15, %eax
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}
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define i32 @test7(i32 %x) nounwind {
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