mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 11:13:28 +01:00
transition to using let instead of set
llvm-svn: 7564
This commit is contained in:
Chris Lattner
parent
7ca890525d
commit
0d7b042206
@ -5,7 +5,7 @@
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//
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//===----------------------------------------------------------------------===//
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// Get the target independent interfaces which we are implementing...
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// Get the target-independent interfaces which we are implementing...
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//
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include "../Target.td"
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@ -22,24 +22,24 @@ include "X86RegisterInfo.td"
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include "X86InstrInfo.td"
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def X86InstrInfo : InstrInfo {
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set PHIInst = PHI;
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set NOOPInst = NOOP;
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let PHIInst = PHI;
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let NOOPInst = NOOP;
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// Define how we want to layout our TargetSpecific information field... This
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// should be kept up-to-date with the fields in the X86InstrInfo.h file.
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set TSFlagsFields = ["FormBits", "isVoid", "hasOpSizePrefix", "Prefix",
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let TSFlagsFields = ["FormBits", "hasOpSizePrefix", "Prefix",
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"TypeBits", "FPFormBits", "printImplicitUses", "Opcode"];
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set TSFlagsShifts = [ 0, 5, 6, 7,
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let TSFlagsShifts = [ 0, 6, 7,
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11, 14, 17, 18];
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}
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def X86 : Target {
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// Specify the callee saved registers.
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set CalleeSavedRegisters = [ESI, EDI, EBX, EBP];
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let CalleeSavedRegisters = [ESI, EDI, EBX, EBP];
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// Yes, pointers are 32-bits in size.
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set PointerType = i32;
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let PointerType = i32;
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// Information about the instructions...
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set InstructionSet = X86InstrInfo;
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let InstructionSet = X86InstrInfo;
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}
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@ -6,8 +6,6 @@
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//
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//===----------------------------------------------------------------------===//
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// Format specifies the encoding used by the instruction. This is part of the
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// ad-hoc solution used to emit machine instruction encodings by our machine
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// code emitter.
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@ -55,9 +53,9 @@ def SpecialFP : FPFormat<5>;
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class X86Inst<string nam, bits<8> opcod, Format f, ArgType a> : Instruction {
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set Namespace = "X86";
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let Namespace = "X86";
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set Name = nam;
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let Name = nam;
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bits<8> Opcode = opcod;
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Format Form = f;
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bits<5> FormBits = Form.Value;
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@ -65,7 +63,6 @@ class X86Inst<string nam, bits<8> opcod, Format f, ArgType a> : Instruction {
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bits<3> TypeBits = Type.Value;
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// Attributes specific to X86 instructions...
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bit isVoid = 0; // Does this inst ignore the return value?
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bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
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bit printImplicitUses = 0; // Should we print implicit uses of this inst?
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@ -101,8 +98,7 @@ class DF { bits<4> Prefix = 9; }
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def PHI : X86Inst<"PHI", 0, Pseudo, NoArg>; // PHI node...
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set isVoid = 1 in
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def NOOP : X86Inst<"nop", 0x90, RawFrm, NoArg>; // nop
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def NOOP : X86Inst<"nop", 0x90, RawFrm, NoArg>; // nop
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def ADJCALLSTACKDOWN : X86Inst<"ADJCALLSTACKDOWN", 0, Pseudo, NoArg>;
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def ADJCALLSTACKUP : X86Inst<"ADJCALLSTACKUP", 0, Pseudo, NoArg>;
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@ -113,11 +109,11 @@ def IMPLICIT_USE : X86Inst<"IMPLICIT_USE", 0, Pseudo, NoArg>;
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//
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// Return instruction...
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set isTerminator = 1, isVoid = 1, isReturn = 1 in
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let isTerminator = 1, isReturn = 1 in
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def RET : X86Inst<"ret", 0xC3, RawFrm, NoArg>;
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// All branches are RawFrm, Void, Branch, and Terminators
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set isVoid = 1, isBranch = 1, isTerminator = 1 in
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let isBranch = 1, isTerminator = 1 in
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class IBr<string name, bits<8> opcode> : X86Inst<name, opcode, RawFrm, NoArg>;
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def JMP : IBr<"jmp", 0xE9>;
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@ -136,9 +132,9 @@ def JG : IBr<"jg" , 0x8F>, TB;
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//===----------------------------------------------------------------------===//
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// Call Instructions...
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//
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set isCall = 1, isVoid = 1 in
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let isCall = 1 in
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// All calls clobber the non-callee saved registers...
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set Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6] in {
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let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6] in {
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def CALLpcrel32 : X86Inst<"call", 0xE8, RawFrm, NoArg>;
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def CALLr32 : X86Inst<"call", 0xFF, MRMS2r, Arg32>;
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def CALLm32 : X86Inst<"call", 0xFF, MRMS2m, Arg32>;
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@ -150,7 +146,7 @@ set isCall = 1, isVoid = 1 in
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//
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def LEAVE : X86Inst<"leave", 0xC9, RawFrm, NoArg>, Imp<[EBP], [EBP]>;
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set isTwoAddress = 1 in // R32 = bswap R32
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let isTwoAddress = 1 in // R32 = bswap R32
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def BSWAPr32 : X86Inst<"bswap", 0xC8, AddRegFrm, Arg32>, TB;
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def XCHGrr8 : X86Inst<"xchg", 0x86, MRMDestReg, Arg8>; // xchg R8, R8
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@ -177,42 +173,39 @@ def MOVmr8 : X86Inst<"mov", 0x8A, MRMSrcMem , Arg8>; // R8 = [mem]
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def MOVmr16 : X86Inst<"mov", 0x8B, MRMSrcMem , Arg16>, OpSize; // R16 = [mem]
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def MOVmr32 : X86Inst<"mov", 0x8B, MRMSrcMem , Arg32>; // R32 = [mem]
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set isVoid = 1 in {
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def MOVrm8 : X86Inst<"mov", 0x88, MRMDestMem, Arg8>; // R8 = [mem]
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def MOVrm16 : X86Inst<"mov", 0x89, MRMDestMem, Arg16>, OpSize; // R16 = [mem]
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def MOVrm32 : X86Inst<"mov", 0x89, MRMDestMem, Arg32>; // R32 = [mem]
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}
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def MOVrm8 : X86Inst<"mov", 0x88, MRMDestMem, Arg8>; // [mem] = R8
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def MOVrm16 : X86Inst<"mov", 0x89, MRMDestMem, Arg16>, OpSize; // [mem] = R16
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def MOVrm32 : X86Inst<"mov", 0x89, MRMDestMem, Arg32>; // [mem] = R32
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//===----------------------------------------------------------------------===//
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// Fixed-Register Multiplication and Division Instructions...
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//
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set isVoid = 1 in {
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// Extra precision multiplication
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def MULr8 : X86Inst<"mul", 0xF6, MRMS4r, Arg8 >, Imp<[AL],[AX]>; // AL,AH = AL*R8
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def MULr16 : X86Inst<"mul", 0xF7, MRMS4r, Arg16>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
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def MULr32 : X86Inst<"mul", 0xF7, MRMS4r, Arg32>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
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// unsigned division/remainder
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def DIVr8 : X86Inst<"div", 0xF6, MRMS6r, Arg8 >, Imp<[AX],[AX]>; // AX/r8 = AL,AH
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def DIVr16 : X86Inst<"div", 0xF7, MRMS6r, Arg16>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
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def DIVr32 : X86Inst<"div", 0xF7, MRMS6r, Arg32>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
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// Extra precision multiplication
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def MULr8 : X86Inst<"mul", 0xF6, MRMS4r, Arg8 >, Imp<[AL],[AX]>; // AL,AH = AL*R8
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def MULr16 : X86Inst<"mul", 0xF7, MRMS4r, Arg16>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
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def MULr32 : X86Inst<"mul", 0xF7, MRMS4r, Arg32>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
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// signed division/remainder
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def IDIVr8 : X86Inst<"idiv",0xF6, MRMS7r, Arg8 >, Imp<[AX],[AX]>; // AX/r8 = AL,AH
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def IDIVr16: X86Inst<"idiv",0xF7, MRMS7r, Arg16>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
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def IDIVr32: X86Inst<"idiv",0xF7, MRMS7r, Arg32>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
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// unsigned division/remainder
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def DIVr8 : X86Inst<"div", 0xF6, MRMS6r, Arg8 >, Imp<[AX],[AX]>; // AX/r8 = AL,AH
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def DIVr16 : X86Inst<"div", 0xF7, MRMS6r, Arg16>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
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def DIVr32 : X86Inst<"div", 0xF7, MRMS6r, Arg32>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
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// Sign-extenders for division
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def CBW : X86Inst<"cbw", 0x98, RawFrm, Arg8 >, Imp<[AL],[AH]>; // AX = signext(AL)
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def CWD : X86Inst<"cwd", 0x99, RawFrm, Arg8 >, Imp<[AX],[DX]>; // DX:AX = signext(AX)
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def CDQ : X86Inst<"cdq", 0x99, RawFrm, Arg8 >, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
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}
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// signed division/remainder
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def IDIVr8 : X86Inst<"idiv",0xF6, MRMS7r, Arg8 >, Imp<[AX],[AX]>; // AX/r8 = AL,AH
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def IDIVr16: X86Inst<"idiv",0xF7, MRMS7r, Arg16>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
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def IDIVr32: X86Inst<"idiv",0xF7, MRMS7r, Arg32>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
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// Sign-extenders for division
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def CBW : X86Inst<"cbw", 0x98, RawFrm, Arg8 >, Imp<[AL],[AH]>; // AX = signext(AL)
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def CWD : X86Inst<"cwd", 0x99, RawFrm, Arg8 >, Imp<[AX],[DX]>; // DX:AX = signext(AX)
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def CDQ : X86Inst<"cdq", 0x99, RawFrm, Arg8 >, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
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//===----------------------------------------------------------------------===//
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// Two address Instructions...
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//
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set isTwoAddress = 1 in { // Define some helper classes to make defs shorter.
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let isTwoAddress = 1 in { // Define some helper classes to make defs shorter.
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class I2A8 <string n, bits<8> o, Format F> : X86Inst<n, o, F, Arg8>;
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class I2A16<string n, bits<8> o, Format F> : X86Inst<n, o, F, Arg16>;
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class I2A32<string n, bits<8> o, Format F> : X86Inst<n, o, F, Arg32>;
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@ -237,8 +230,8 @@ def SUBri32 : I2A32<"sub", 0x81, MRMS5r >; // R32 -= imm32
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def SBBrr32 : I2A32<"sbb", 0x19, MRMDestReg>; // R32 -= R32+Carry
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def IMULr16 : I2A16<"imul", 0xAF, MRMSrcReg>, TB, OpSize; // R16 *= R16
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def IMULr32 : I2A32<"imul", 0xAF, MRMSrcReg>, TB; // R32 *= R32
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def IMULr16 : I2A16<"imul", 0xAF, MRMSrcReg>, TB, OpSize; // R16 *= R16
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def IMULr32 : I2A32<"imul", 0xAF, MRMSrcReg>, TB; // R32 *= R32
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// Logical operators...
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def ANDrr8 : I2A8 <"and", 0x20, MRMDestReg>; // R8 &= R8
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@ -316,14 +309,12 @@ def CMOVErr16 : I2A16<"cmove", 0x44, MRMSrcReg>, TB, OpSize; // if ==, R1
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def CMOVNErr32: I2A32<"cmovne",0x45, MRMSrcReg>, TB; // if !=, R32 = R32
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// Integer comparisons
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set isVoid = 1 in {
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def CMPrr8 : X86Inst<"cmp", 0x38, MRMDestReg, Arg8 >; // compare R8, R8
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def CMPrr16 : X86Inst<"cmp", 0x39, MRMDestReg, Arg16>, OpSize; // compare R16, R16
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def CMPrr32 : X86Inst<"cmp", 0x39, MRMDestReg, Arg32>; // compare R32, R32
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def CMPri8 : X86Inst<"cmp", 0x80, MRMS7r , Arg8 >; // compare R8, imm8
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def CMPri16 : X86Inst<"cmp", 0x81, MRMS7r , Arg16>, OpSize; // compare R16, imm16
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def CMPri32 : X86Inst<"cmp", 0x81, MRMS7r , Arg32>; // compare R32, imm32
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}
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def CMPrr8 : X86Inst<"cmp", 0x38, MRMDestReg, Arg8 >; // compare R8, R8
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def CMPrr16 : X86Inst<"cmp", 0x39, MRMDestReg, Arg16>, OpSize; // compare R16, R16
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def CMPrr32 : X86Inst<"cmp", 0x39, MRMDestReg, Arg32>; // compare R32, R32
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def CMPri8 : X86Inst<"cmp", 0x80, MRMS7r , Arg8 >; // compare R8, imm8
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def CMPri16 : X86Inst<"cmp", 0x81, MRMS7r , Arg16>, OpSize; // compare R16, imm16
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def CMPri32 : X86Inst<"cmp", 0x81, MRMS7r , Arg32>; // compare R32, imm32
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// Sign/Zero extenders
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def MOVSXr16r8 : X86Inst<"movsx", 0xBE, MRMSrcReg, Arg8>, TB, OpSize; // R16 = signext(R8)
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@ -342,7 +333,7 @@ def MOVZXr32r16: X86Inst<"movzx", 0xB7, MRMSrcReg, Arg8>, TB; // R32 = z
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// Floating point pseudo instructions...
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class FPInst<string n, bits<8> o, Format F, ArgType t, FPFormat fp>
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: X86Inst<n, o, F, t> { set FPForm = fp; set FPFormBits = FPForm.Value; }
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: X86Inst<n, o, F, t> { let FPForm = fp; let FPFormBits = FPForm.Value; }
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def FpMOV : FPInst<"FMOV", 0, Pseudo, ArgF80, SpecialFP>; // f1 = fmov f2
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def FpADD : FPInst<"FADD", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fadd f2, f3
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@ -350,40 +341,36 @@ def FpSUB : FPInst<"FSUB", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fsub f2, f3
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def FpMUL : FPInst<"FMUL", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fmul f2, f3
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def FpDIV : FPInst<"FDIV", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fdiv f2, f3
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set isVoid = 1 in
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def FpUCOM : FPInst<"FUCOM", 0, Pseudo, ArgF80, TwoArgFP>; // FPSW = fucom f1, f2
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def FpUCOM : FPInst<"FUCOM", 0, Pseudo, ArgF80, TwoArgFP>; // FPSW = fucom f1, f2
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def FpGETRESULT : FPInst<"FGETRESULT",0, Pseudo, ArgF80, SpecialFP>; // FPR = ST(0)
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set isVoid = 1 in
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def FpSETRESULT : FPInst<"FSETRESULT",0, Pseudo, ArgF80, SpecialFP>; // ST(0) = FPR
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def FpSETRESULT : FPInst<"FSETRESULT",0, Pseudo, ArgF80, SpecialFP>; // ST(0) = FPR
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// Floating point loads & stores...
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def FLDrr : FPInst<"fld" , 0xC0, AddRegFrm, ArgF80, NotFP>, D9; // push(ST(i))
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def FLDr32 : FPInst<"fld" , 0xD9, MRMS0m , ArgF32, ZeroArgFP>; // load float
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def FLDr64 : FPInst<"fld" , 0xDD, MRMS0m , ArgF64, ZeroArgFP>; // load double
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def FLDr80 : FPInst<"fld" , 0xDB, MRMS5m , ArgF80, ZeroArgFP>; // load extended
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def FILDr16 : FPInst<"fild" , 0xDF, MRMS0m , Arg16 , ZeroArgFP>; // load signed short
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def FILDr32 : FPInst<"fild" , 0xDB, MRMS0m , Arg32 , ZeroArgFP>; // load signed int
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def FILDr64 : FPInst<"fild" , 0xDF, MRMS5m , Arg64 , ZeroArgFP>; // load signed long
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def FLDr32 : FPInst<"fld" , 0xD9, MRMS0m , ArgF32, ZeroArgFP>; // load float
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def FLDr64 : FPInst<"fld" , 0xDD, MRMS0m , ArgF64, ZeroArgFP>; // load double
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def FLDr80 : FPInst<"fld" , 0xDB, MRMS5m , ArgF80, ZeroArgFP>; // load extended
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def FILDr16 : FPInst<"fild" , 0xDF, MRMS0m , Arg16 , ZeroArgFP>; // load signed short
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def FILDr32 : FPInst<"fild" , 0xDB, MRMS0m , Arg32 , ZeroArgFP>; // load signed int
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def FILDr64 : FPInst<"fild" , 0xDF, MRMS5m , Arg64 , ZeroArgFP>; // load signed long
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set isVoid = 1 in {
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def FSTr32 : FPInst<"fst" , 0xD9, MRMS2m , ArgF32, OneArgFP>; // store float
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def FSTr64 : FPInst<"fst" , 0xDD, MRMS2m , ArgF64, OneArgFP>; // store double
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def FSTPr32 : FPInst<"fstp", 0xD9, MRMS3m , ArgF32, OneArgFP>; // store float, pop
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def FSTPr64 : FPInst<"fstp", 0xDD, MRMS3m , ArgF64, OneArgFP>; // store double, pop
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def FSTPr80 : FPInst<"fstp", 0xDB, MRMS7m , ArgF80, OneArgFP>; // store extended, pop
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def FSTrr : FPInst<"fst" , 0xD0, AddRegFrm, ArgF80, NotFP >, DD; // ST(i) = ST(0)
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def FSTPrr : FPInst<"fstp", 0xD8, AddRegFrm, ArgF80, NotFP >, DD; // ST(i) = ST(0), pop
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def FSTr32 : FPInst<"fst" , 0xD9, MRMS2m , ArgF32, OneArgFP>; // store float
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def FSTr64 : FPInst<"fst" , 0xDD, MRMS2m , ArgF64, OneArgFP>; // store double
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def FSTPr32 : FPInst<"fstp", 0xD9, MRMS3m , ArgF32, OneArgFP>; // store float, pop
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def FSTPr64 : FPInst<"fstp", 0xDD, MRMS3m , ArgF64, OneArgFP>; // store double, pop
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def FSTPr80 : FPInst<"fstp", 0xDB, MRMS7m , ArgF80, OneArgFP>; // store extended, pop
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def FSTrr : FPInst<"fst" , 0xD0, AddRegFrm, ArgF80, NotFP >, DD; // ST(i) = ST(0)
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def FSTPrr : FPInst<"fstp", 0xD8, AddRegFrm, ArgF80, NotFP >, DD; // ST(i) = ST(0), pop
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def FISTr16 : FPInst<"fist", 0xDF, MRMS2m, Arg16 , OneArgFP>; // store signed short
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def FISTr32 : FPInst<"fist", 0xDB, MRMS2m, Arg32 , OneArgFP>; // store signed int
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def FISTPr16 : FPInst<"fistp", 0xDF, MRMS3m, Arg16 , NotFP >; // store signed short, pop
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def FISTPr32 : FPInst<"fistp", 0xDB, MRMS3m, Arg32 , NotFP >; // store signed int, pop
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def FISTPr64 : FPInst<"fistpll", 0xDF, MRMS7m, Arg64 , OneArgFP>; // store signed long, pop
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def FISTr16 : FPInst<"fist", 0xDF, MRMS2m, Arg16 , OneArgFP>; // store signed short
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def FISTr32 : FPInst<"fist", 0xDB, MRMS2m, Arg32 , OneArgFP>; // store signed int
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def FISTPr16 : FPInst<"fistp", 0xDF, MRMS3m, Arg16 , NotFP >; // store signed short, pop
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def FISTPr32 : FPInst<"fistp", 0xDB, MRMS3m, Arg32 , NotFP >; // store signed int, pop
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def FISTPr64 : FPInst<"fistpll", 0xDF, MRMS7m, Arg64 , OneArgFP>; // store signed long, pop
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def FXCH : FPInst<"fxch", 0xC8, AddRegFrm, ArgF80, NotFP>, D9; // fxch ST(i), ST(0)
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}
|
||||
def FXCH : FPInst<"fxch", 0xC8, AddRegFrm, ArgF80, NotFP>, D9; // fxch ST(i), ST(0)
|
||||
|
||||
// Floating point constant loads...
|
||||
def FLD0 : FPInst<"fldz", 0xEE, RawFrm, ArgF80, ZeroArgFP>, D9;
|
||||
@ -430,13 +417,11 @@ def FDIVRrST0 : FPrST0Inst <"fdivr", 0xF0>; // ST(i) = ST(0) / ST(i)
|
||||
def FDIVRPrST0 : FPrST0PInst<"fdivrp", 0xF0>; // ST(i) = ST(0) / ST(i), pop
|
||||
|
||||
// Floating point compares
|
||||
set isVoid = 1 in {
|
||||
def FUCOMr : X86Inst<"fucom" , 0xE0, AddRegFrm, ArgF80>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i)
|
||||
def FUCOMPr : X86Inst<"fucomp" , 0xE8, AddRegFrm, ArgF80>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i), pop
|
||||
def FUCOMPPr : X86Inst<"fucompp", 0xE9, RawFrm , ArgF80>, DA, Imp<[ST0],[]>; // compare ST(0) with ST(1), pop, pop
|
||||
def FUCOMr : X86Inst<"fucom" , 0xE0, AddRegFrm, ArgF80>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i)
|
||||
def FUCOMPr : X86Inst<"fucomp" , 0xE8, AddRegFrm, ArgF80>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i), pop
|
||||
def FUCOMPPr : X86Inst<"fucompp", 0xE9, RawFrm , ArgF80>, DA, Imp<[ST0],[]>; // compare ST(0) with ST(1), pop, pop
|
||||
|
||||
// Floating point flag ops
|
||||
def FNSTSWr8 : X86Inst<"fnstsw" , 0xE0, RawFrm , ArgF80>, DF, Imp<[],[AX]>; // AX = fp flags
|
||||
def FNSTCWm16 : X86Inst<"fnstcw" , 0xD9, MRMS7m , Arg16 >; // [mem16] = X87 control world
|
||||
def FLDCWm16 : X86Inst<"fldcw" , 0xD9, MRMS5m , Arg16 >; // X87 control world = [mem16]
|
||||
}
|
||||
// Floating point flag ops
|
||||
def FNSTSWr8 : X86Inst<"fnstsw" , 0xE0, RawFrm , ArgF80>, DF, Imp<[],[AX]>; // AX = fp flags
|
||||
def FNSTCWm16 : X86Inst<"fnstcw" , 0xD9, MRMS7m , Arg16 >; // [mem16] = X87 control world
|
||||
def FLDCWm16 : X86Inst<"fldcw" , 0xD9, MRMS5m , Arg16 >; // X87 control world = [mem16]
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Register definitions...
|
||||
//
|
||||
set Namespace = "X86" in {
|
||||
let Namespace = "X86" in {
|
||||
// 32-bit registers
|
||||
def EAX : Register; def ECX : Register;
|
||||
def EDX : Register; def EBX : Register;
|
||||
@ -71,7 +71,7 @@ def : RegisterAliases<SP, [ESP]>; def : RegisterAliases<BP, [EBP]>;
|
||||
//
|
||||
def r8 : RegisterClass<i8, 1, [AL, CL, DL, BL, AH, CH, DH, BH]>;
|
||||
def r16 : RegisterClass<i16, 2, [AX, CX, DX, BX, SI, DI, BP, SP]> {
|
||||
set Methods = [{
|
||||
let Methods = [{
|
||||
iterator allocation_order_end(MachineFunction &MF) const {
|
||||
if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
|
||||
return end()-2; // If so, don't allocate SP or BP
|
||||
@ -82,7 +82,7 @@ def r16 : RegisterClass<i16, 2, [AX, CX, DX, BX, SI, DI, BP, SP]> {
|
||||
}
|
||||
|
||||
def r32 : RegisterClass<i32, 4, [EAX, ECX, EDX, EBX, ESI, EDI, EBP, ESP]> {
|
||||
set Methods = [{
|
||||
let Methods = [{
|
||||
iterator allocation_order_end(MachineFunction &MF) const {
|
||||
if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
|
||||
return end()-2; // If so, don't allocate ESP or EBP
|
||||
|
||||
Loading…
Reference in New Issue
Block a user