mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-25 04:02:41 +01:00
Fix support to use NEON for single precision fp math.
llvm-svn: 78397
This commit is contained in:
Evan Cheng
parent
7ded8b7bdf
commit
0dab4cc8a0
@ -587,7 +587,7 @@ ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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}
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break;
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case ARM::FSTD:
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case ARM::FSTS:
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case ARM::FSTS:
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if (MI->getOperand(1).isFI() &&
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MI->getOperand(2).isImm() &&
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MI->getOperand(2).getImm() == 0) {
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@ -610,8 +610,10 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (DestRC != SrcRC) {
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if (((DestRC == ARM::DPRRegisterClass) && (SrcRC == ARM::DPR_VFP2RegisterClass)) ||
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((SrcRC == ARM::DPRRegisterClass) && (DestRC == ARM::DPR_VFP2RegisterClass))) {
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if (((DestRC == ARM::DPRRegisterClass) &&
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(SrcRC == ARM::DPR_VFP2RegisterClass)) ||
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((SrcRC == ARM::DPRRegisterClass) &&
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(DestRC == ARM::DPR_VFP2RegisterClass))) {
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// Allow copy between DPR and DPR_VFP2.
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} else {
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return false;
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@ -648,7 +650,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addReg(0).addImm(0));
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} else if (RC == ARM::DPRRegisterClass) {
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} else if (RC == ARM::DPRRegisterClass || RC == ARM::DPR_VFP2RegisterClass) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0));
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@ -670,7 +672,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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if (RC == ARM::GPRRegisterClass) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
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.addFrameIndex(FI).addReg(0).addImm(0));
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} else if (RC == ARM::DPRRegisterClass) {
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} else if (RC == ARM::DPRRegisterClass || RC == ARM::DPR_VFP2RegisterClass) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
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.addFrameIndex(FI).addImm(0));
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} else {
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@ -334,13 +334,18 @@ class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
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[(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
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// Basic 2-register operations, scalar single-precision
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class N2VDInts<SDNode OpNode, NeonI Inst>
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class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
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bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
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ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
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: N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
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(outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
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!strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
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class N2VDIntsPat<SDNode OpNode, NeonI Inst>
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: NEONFPPat<(f32 (OpNode SPR:$a)),
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(EXTRACT_SUBREG (COPY_TO_REGCLASS
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(Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
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SPR:$a, arm_ssubreg_0)),
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DPR_VFP2),
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arm_ssubreg_0)>;
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(EXTRACT_SUBREG
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(Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
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arm_ssubreg_0)>;
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// Narrow 2-register intrinsics.
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class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
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@ -380,15 +385,20 @@ class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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}
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// Basic 3-register operations, scalar single-precision
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class N3VDs<SDNode OpNode, NeonI Inst>
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class N3VDs<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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string OpcodeStr, ValueType ResTy, ValueType OpTy,
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SDNode OpNode, bit Commutable>
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: N3V<op24, op23, op21_20, op11_8, 0, op4,
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(outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), NoItinerary,
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!strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", []> {
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let isCommutable = Commutable;
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}
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class N3VDsPat<SDNode OpNode, NeonI Inst>
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: NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
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(EXTRACT_SUBREG (COPY_TO_REGCLASS
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(Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
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SPR:$a, arm_ssubreg_0),
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(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
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SPR:$b, arm_ssubreg_0)),
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DPR_VFP2),
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arm_ssubreg_0)>;
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(EXTRACT_SUBREG
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(Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
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(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
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arm_ssubreg_0)>;
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// Basic 3-register intrinsics, both double- and quad-register.
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class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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@ -427,18 +437,20 @@ class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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(Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
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// Multiply-Add/Sub operations, scalar single-precision
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class N3VDMulOps<SDNode MulNode, SDNode OpNode, NeonI Inst>
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: NEONFPPat<(f32 (OpNode SPR:$acc,
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(f32 (MulNode SPR:$a, SPR:$b)))),
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(EXTRACT_SUBREG (COPY_TO_REGCLASS
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(Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
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SPR:$acc, arm_ssubreg_0),
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(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
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SPR:$a, arm_ssubreg_0),
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(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
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SPR:$b, arm_ssubreg_0)),
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DPR_VFP2),
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arm_ssubreg_0)>;
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class N3VDMulOps<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
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: N3V<op24, op23, op21_20, op11_8, 0, op4,
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(outs DPR_VFP2:$dst),
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(ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), NoItinerary,
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!strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", []>;
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class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
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: NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
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(EXTRACT_SUBREG
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(Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0),
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(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
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(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
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arm_ssubreg_0)>;
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// Neon 3-argument intrinsics, both double- and quad-register.
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// The destination register is also used as the first source operand register.
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@ -1011,9 +1023,6 @@ defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
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// VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
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defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
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// Vector Add Operations used for single-precision FP
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def : N3VDs<fadd, VADDfd>;
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// Vector Multiply Operations.
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// VMUL : Vector Multiply (integer, polynomial and floating-point)
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@ -1036,9 +1045,6 @@ def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, "vmull.p8", v8i16, v8i8,
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// VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
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defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, "vqdmull.s", int_arm_neon_vqdmull, 1>;
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// Vector Multiply Operations used for single-precision FP
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def : N3VDs<fmul, VMULfd>;
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// Vector Multiply-Accumulate and Multiply-Subtract Operations.
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// VMLA : Vector Multiply Accumulate (integer and floating-point)
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@ -1060,10 +1066,6 @@ defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
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// VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
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defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
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// Vector Multiply-Accumulate/Subtract used for single-precision FP
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def : N3VDMulOps<fmul, fadd, VMLAfd>;
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def : N3VDMulOps<fmul, fsub, VMLSfd>;
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// Vector Subtract Operations.
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// VSUB : Vector Subtract (integer and floating-point)
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@ -1087,9 +1089,6 @@ defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
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// VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
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defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
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// Vector Sub Operations used for single-precision FP
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def : N3VDs<fsub, VSUBfd>;
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// Vector Comparisons.
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// VCEQ : Vector Compare Equal
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@ -1453,7 +1452,6 @@ def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
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v2f32, v2f32, int_arm_neon_vabsf>;
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def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
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v4f32, v4f32, int_arm_neon_vabsf>;
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def : N2VDInts<fabs, VABSfd>;
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// VQABS : Vector Saturating Absolute Value
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defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s",
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@ -1492,7 +1490,6 @@ def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
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(outs QPR:$dst), (ins QPR:$src), NoItinerary,
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"vneg.f32\t$dst, $src", "",
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[(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
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def : N2VDInts<fneg, VNEGf32d>;
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def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
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def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
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@ -1906,6 +1903,51 @@ class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
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def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
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def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
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//===----------------------------------------------------------------------===//
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// NEON instructions for single-precision FP math
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//===----------------------------------------------------------------------===//
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// These need separate instructions because they must use DPR_VFP2 register
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// class which have SPR sub-registers.
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// Vector Add Operations used for single-precision FP
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let neverHasSideEffects = 1 in
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def VADDfd_sfp : N3VDs<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd,1>;
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def : N3VDsPat<fadd, VADDfd_sfp>;
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// Vector Multiply Operations used for single-precision FP
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let neverHasSideEffects = 1 in
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def VMULfd_sfp : N3VDs<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul,1>;
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def : N3VDsPat<fmul, VMULfd_sfp>;
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// Vector Multiply-Accumulate/Subtract used for single-precision FP
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let neverHasSideEffects = 1 in
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def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32,fmul,fadd>;
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def : N3VDMulOpsPat<fmul, fadd, VMLAfd>;
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let neverHasSideEffects = 1 in
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def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32,fmul,fsub>;
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def : N3VDMulOpsPat<fmul, fsub, VMLSfd>;
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// Vector Sub Operations used for single-precision FP
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let neverHasSideEffects = 1 in
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def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub,0>;
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def : N3VDsPat<fsub, VSUBfd_sfp>;
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// Vector Absolute for single-precision FP
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let neverHasSideEffects = 1 in
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def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
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v2f32, v2f32, int_arm_neon_vabsf>;
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def : N2VDIntsPat<fabs, VABSfd_sfp>;
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// Vector Negate for single-precision FP
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let neverHasSideEffects = 1 in
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def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
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(outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
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"vneg.f32\t$dst, $src", "", []>;
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def : N2VDIntsPat<fneg, VNEGf32d_sfp>;
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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//===----------------------------------------------------------------------===//
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80
test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll
Normal file
80
test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll
Normal file
@ -0,0 +1,80 @@
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; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8 -mattr=+neonfp
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%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
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%struct.JHUFF_TBL = type { [17 x i8], [256 x i8], i32 }
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%struct.JQUANT_TBL = type { [64 x i16], i32 }
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%struct.__sFILEX = type opaque
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%struct.__sbuf = type { i8*, i32 }
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%struct.anon = type { [8 x i32], [48 x i8] }
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%struct.backing_store_info = type { void (%struct.jpeg_common_struct*, %struct.backing_store_info*, i8*, i32, i32)*, void (%struct.jpeg_common_struct*, %struct.backing_store_info*, i8*, i32, i32)*, void (%struct.jpeg_common_struct*, %struct.backing_store_info*)*, %struct.FILE*, [64 x i8] }
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%struct.jpeg_color_deconverter = type { void (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*, i8***, i32, i8**, i32)* }
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%struct.jpeg_color_quantizer = type { void (%struct.jpeg_decompress_struct*, i32)*, void (%struct.jpeg_decompress_struct*, i8**, i8**, i32)*, void (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*)* }
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%struct.jpeg_common_struct = type { %struct.jpeg_error_mgr*, %struct.jpeg_memory_mgr*, %struct.jpeg_progress_mgr*, i32, i32 }
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%struct.jpeg_component_info = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.JQUANT_TBL*, i8* }
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%struct.jpeg_d_coef_controller = type { void (%struct.jpeg_decompress_struct*)*, i32 (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*)*, i32 (%struct.jpeg_decompress_struct*, i8***)*, %struct.jvirt_barray_control** }
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%struct.jpeg_d_main_controller = type { void (%struct.jpeg_decompress_struct*, i32)*, void (%struct.jpeg_decompress_struct*, i8**, i32*, i32)* }
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%struct.jpeg_d_post_controller = type { void (%struct.jpeg_decompress_struct*, i32)*, void (%struct.jpeg_decompress_struct*, i8***, i32*, i32, i8**, i32*, i32)* }
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%struct.jpeg_decomp_master = type { void (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*)*, i32 }
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%struct.jpeg_decompress_struct = type { %struct.jpeg_error_mgr*, %struct.jpeg_memory_mgr*, %struct.jpeg_progress_mgr*, i32, i32, %struct.jpeg_source_mgr*, i32, i32, i32, i32, i32, i32, i32, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8**, i32, i32, i32, i32, i32, [64 x i32]*, [4 x %struct.JQUANT_TBL*], [4 x %struct.JHUFF_TBL*], [4 x %struct.JHUFF_TBL*], i32, %struct.jpeg_component_info*, i32, i32, [16 x i8], [16 x i8], [16 x i8], i32, i32, i8, i16, i16, i32, i8, i32, i32, i32, i32, i32, i8*, i32, [4 x %struct.jpeg_component_info*], i32, i32, i32, [10 x i32], i32, i32, i32, i32, i32, %struct.jpeg_decomp_master*, %struct.jpeg_d_main_controller*, %struct.jpeg_d_coef_controller*, %struct.jpeg_d_post_controller*, %struct.jpeg_input_controller*, %struct.jpeg_marker_reader*, %struct.jpeg_entropy_decoder*, %struct.jpeg_inverse_dct*, %struct.jpeg_upsampler*, %struct.jpeg_color_deconverter*, %struct.jpeg_color_quantizer* }
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%struct.jpeg_entropy_decoder = type { void (%struct.jpeg_decompress_struct*)*, i32 (%struct.jpeg_decompress_struct*, [64 x i16]**)* }
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%struct.jpeg_error_mgr = type { void (%struct.jpeg_common_struct*)*, void (%struct.jpeg_common_struct*, i32)*, void (%struct.jpeg_common_struct*)*, void (%struct.jpeg_common_struct*, i8*)*, void (%struct.jpeg_common_struct*)*, i32, %struct.anon, i32, i32, i8**, i32, i8**, i32, i32 }
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%struct.jpeg_input_controller = type { i32 (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*)*, i32, i32 }
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%struct.jpeg_inverse_dct = type { void (%struct.jpeg_decompress_struct*)*, [10 x void (%struct.jpeg_decompress_struct*, %struct.jpeg_component_info*, i16*, i8**, i32)*] }
|
||||
%struct.jpeg_marker_reader = type { void (%struct.jpeg_decompress_struct*)*, i32 (%struct.jpeg_decompress_struct*)*, i32 (%struct.jpeg_decompress_struct*)*, i32 (%struct.jpeg_decompress_struct*)*, [16 x i32 (%struct.jpeg_decompress_struct*)*], i32, i32, i32, i32 }
|
||||
%struct.jpeg_memory_mgr = type { i8* (%struct.jpeg_common_struct*, i32, i32)*, i8* (%struct.jpeg_common_struct*, i32, i32)*, i8** (%struct.jpeg_common_struct*, i32, i32, i32)*, [64 x i16]** (%struct.jpeg_common_struct*, i32, i32, i32)*, %struct.jvirt_sarray_control* (%struct.jpeg_common_struct*, i32, i32, i32, i32, i32)*, %struct.jvirt_barray_control* (%struct.jpeg_common_struct*, i32, i32, i32, i32, i32)*, void (%struct.jpeg_common_struct*)*, i8** (%struct.jpeg_common_struct*, %struct.jvirt_sarray_control*, i32, i32, i32)*, [64 x i16]** (%struct.jpeg_common_struct*, %struct.jvirt_barray_control*, i32, i32, i32)*, void (%struct.jpeg_common_struct*, i32)*, void (%struct.jpeg_common_struct*)*, i32 }
|
||||
%struct.jpeg_progress_mgr = type { void (%struct.jpeg_common_struct*)*, i32, i32, i32, i32 }
|
||||
%struct.jpeg_source_mgr = type { i8*, i32, void (%struct.jpeg_decompress_struct*)*, i32 (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*, i32)*, i32 (%struct.jpeg_decompress_struct*, i32)*, void (%struct.jpeg_decompress_struct*)* }
|
||||
%struct.jpeg_upsampler = type { void (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*, i8***, i32*, i32, i8**, i32*, i32)*, i32 }
|
||||
%struct.jvirt_barray_control = type { [64 x i16]**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.jvirt_barray_control*, %struct.backing_store_info }
|
||||
%struct.jvirt_sarray_control = type { i8**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.jvirt_sarray_control*, %struct.backing_store_info }
|
||||
|
||||
define arm_apcscc void @jpeg_idct_float(%struct.jpeg_decompress_struct* nocapture %cinfo, %struct.jpeg_component_info* nocapture %compptr, i16* nocapture %coef_block, i8** nocapture %output_buf, i32 %output_col) nounwind {
|
||||
entry:
|
||||
br label %bb
|
||||
|
||||
bb: ; preds = %bb, %entry
|
||||
%0 = load float* undef, align 4 ; <float> [#uses=1]
|
||||
%1 = fmul float undef, %0 ; <float> [#uses=2]
|
||||
%tmp73 = add i32 0, 224 ; <i32> [#uses=1]
|
||||
%scevgep74 = getelementptr i8* null, i32 %tmp73 ; <i8*> [#uses=1]
|
||||
%scevgep7475 = bitcast i8* %scevgep74 to float* ; <float*> [#uses=1]
|
||||
%2 = load float* null, align 4 ; <float> [#uses=1]
|
||||
%3 = fmul float 0.000000e+00, %2 ; <float> [#uses=2]
|
||||
%4 = fadd float %1, %3 ; <float> [#uses=1]
|
||||
%5 = fsub float %1, %3 ; <float> [#uses=2]
|
||||
%6 = fadd float undef, 0.000000e+00 ; <float> [#uses=2]
|
||||
%7 = fmul float undef, 0x3FF6A09E60000000 ; <float> [#uses=1]
|
||||
%8 = fsub float %7, %6 ; <float> [#uses=2]
|
||||
%9 = fsub float %4, %6 ; <float> [#uses=1]
|
||||
%10 = fadd float %5, %8 ; <float> [#uses=2]
|
||||
%11 = fsub float %5, %8 ; <float> [#uses=1]
|
||||
%12 = sitofp i16 undef to float ; <float> [#uses=1]
|
||||
%13 = fmul float %12, 0.000000e+00 ; <float> [#uses=2]
|
||||
%14 = sitofp i16 undef to float ; <float> [#uses=1]
|
||||
%15 = load float* %scevgep7475, align 4 ; <float> [#uses=1]
|
||||
%16 = fmul float %14, %15 ; <float> [#uses=2]
|
||||
%17 = fadd float undef, undef ; <float> [#uses=2]
|
||||
%18 = fadd float %13, %16 ; <float> [#uses=2]
|
||||
%19 = fsub float %13, %16 ; <float> [#uses=1]
|
||||
%20 = fadd float %18, %17 ; <float> [#uses=2]
|
||||
%21 = fsub float %18, %17 ; <float> [#uses=1]
|
||||
%22 = fmul float %21, 0x3FF6A09E60000000 ; <float> [#uses=1]
|
||||
%23 = fmul float undef, 0x3FFD906BC0000000 ; <float> [#uses=2]
|
||||
%24 = fmul float %19, 0x3FF1517A80000000 ; <float> [#uses=1]
|
||||
%25 = fsub float %24, %23 ; <float> [#uses=1]
|
||||
%26 = fadd float undef, %23 ; <float> [#uses=1]
|
||||
%27 = fsub float %26, %20 ; <float> [#uses=3]
|
||||
%28 = fsub float %22, %27 ; <float> [#uses=2]
|
||||
%29 = fadd float %25, %28 ; <float> [#uses=1]
|
||||
%30 = fadd float undef, %20 ; <float> [#uses=1]
|
||||
store float %30, float* undef, align 4
|
||||
%31 = fadd float %10, %27 ; <float> [#uses=1]
|
||||
store float %31, float* undef, align 4
|
||||
%32 = fsub float %10, %27 ; <float> [#uses=1]
|
||||
store float %32, float* undef, align 4
|
||||
%33 = fadd float %11, %28 ; <float> [#uses=1]
|
||||
store float %33, float* undef, align 4
|
||||
%34 = fsub float %9, %29 ; <float> [#uses=1]
|
||||
store float %34, float* undef, align 4
|
||||
br label %bb
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user