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[AMDGPU][MC] Added support of 3-element addresses for MIMG instructions

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See bug 35999: https://bugs.llvm.org/show_bug.cgi?id=35999

Differential Revision: https://reviews.llvm.org/D45084

Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 329187
This commit is contained in:
Dmitry Preobrazhensky 2018-04-04 13:01:17 +00:00
parent 295c82336d
commit 0daeb0bf1f
2 changed files with 72 additions and 1 deletions
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10
lib/Target/AMDGPU/MIMGInstructions.td
View File

@ -58,6 +58,8 @@ multiclass MIMG_NoSampler_Src_Helper_Helper <bits<7> op, string asm,
MIMG_Mask<asm#"_V1"#suffix, channels>;
def NAME # _V2 # suffix : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64, d16_bit>,
MIMG_Mask<asm#"_V2"#suffix, channels>;
def NAME # _V3 # suffix : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_96, d16_bit>,
MIMG_Mask<asm#"_V3"#suffix, channels>;
def NAME # _V4 # suffix : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128, d16_bit>,
MIMG_Mask<asm#"_V4"#suffix, channels>;
}
@ -120,6 +122,8 @@ multiclass MIMG_Store_Addr_Helper_Helper <bits<7> op, string asm,
MIMG_Mask<asm#"_V1"#suffix, channels>;
def NAME # _V2 # suffix : MIMG_Store_Helper <op, asm, data_rc, VReg_64, d16_bit>,
MIMG_Mask<asm#"_V2"#suffix, channels>;
def NAME # _V3 # suffix : MIMG_Store_Helper <op, asm, data_rc, VReg_96, d16_bit>,
MIMG_Mask<asm#"_V3"#suffix, channels>;
def NAME # _V4 # suffix : MIMG_Store_Helper <op, asm, data_rc, VReg_128, d16_bit>,
MIMG_Mask<asm#"_V4"#suffix, channels>;
}
@ -224,7 +228,8 @@ multiclass MIMG_Atomic_Addr_Helper_m <mimg op,
// So only one variant can be disassembled. V1 looks the safest to decode.
defm _V1 : MIMG_Atomic_Helper_m <op, name # "_V1", asm, asm # "_V1", data_rc, VGPR_32, is32Bit, enableDasm>;
defm _V2 : MIMG_Atomic_Helper_m <op, name # "_V2", asm, asm # "_V2", data_rc, VReg_64, is32Bit>;
defm _V4 : MIMG_Atomic_Helper_m <op, name # "_V3", asm, asm # "_V3", data_rc, VReg_128, is32Bit>;
defm _V3 : MIMG_Atomic_Helper_m <op, name # "_V3", asm, asm # "_V3", data_rc, VReg_96, is32Bit>;
defm _V4 : MIMG_Atomic_Helper_m <op, name # "_V4", asm, asm # "_V4", data_rc, VReg_128, is32Bit>;
}
multiclass MIMG_Atomic <mimg op, string asm,
@ -262,6 +267,8 @@ multiclass MIMG_Sampler_Src_Helper_Helper <bits<7> op, string asm,
MIMG_Mask<asm#"_V1"#suffix, channels>;
def _V2 # suffix : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm, d16_bit>,
MIMG_Mask<asm#"_V2"#suffix, channels>;
def _V3 # suffix : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_96, wqm, d16_bit>,
MIMG_Mask<asm#"_V3"#suffix, channels>;
def _V4 # suffix : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm, d16_bit>,
MIMG_Mask<asm#"_V4"#suffix, channels>;
def _V8 # suffix : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm, d16_bit>,
@ -334,6 +341,7 @@ multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
string suffix> {
def prefix # _V1 # suffix : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm, d16_bit, "AMDGPU">;
def prefix # _V2 # suffix : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm, d16_bit>;
def prefix # _V3 # suffix : MIMG_Gather_Helper <op, asm, dst_rc, VReg_96, wqm, d16_bit>;
def prefix # _V4 # suffix : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm, d16_bit>;
def prefix # _V8 # suffix : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm, d16_bit>;
def prefix # _V16 # suffix : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm, d16_bit>;

63
test/MC/AMDGPU/mimg.s
View File

@ -19,6 +19,15 @@
image_load v[4:6], v[237:240], s[28:35] dmask:0x7 unorm
// GCN: image_load v[4:6], v[237:240], s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x00,0xf0,0xed,0x04,0x07,0x00]
image_load v4, v237, s[28:35]
// GCN: image_load v4, v237, s[28:35] ; encoding: [0x00,0x00,0x00,0xf0,0xed,0x04,0x07,0x00]
image_load v4, v[237:238], s[28:35]
// GCN: image_load v4, v[237:238], s[28:35] ; encoding: [0x00,0x00,0x00,0xf0,0xed,0x04,0x07,0x00]
image_load v4, v[237:239], s[28:35]
// GCN: image_load v4, v[237:239], s[28:35] ; encoding: [0x00,0x00,0x00,0xf0,0xed,0x04,0x07,0x00]
image_load v4, v[237:240], s[28:35]
// GCN: image_load v4, v[237:240], s[28:35] ; encoding: [0x00,0x00,0x00,0xf0,0xed,0x04,0x07,0x00]
@ -43,6 +52,15 @@ image_load v5, v[1:4], s[8:15] r128
image_store v[193:195], v[237:240], s[28:35] dmask:0x7 unorm
// GCN: image_store v[193:195], v[237:240], s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x20,0xf0,0xed,0xc1,0x07,0x00]
image_store v193, v237, s[28:35]
// GCN: image_store v193, v237, s[28:35] ; encoding: [0x00,0x00,0x20,0xf0,0xed,0xc1,0x07,0x00]
image_store v193, v[237:238], s[28:35]
// GCN: image_store v193, v[237:238], s[28:35] ; encoding: [0x00,0x00,0x20,0xf0,0xed,0xc1,0x07,0x00]
image_store v193, v[237:239], s[28:35]
// GCN: image_store v193, v[237:239], s[28:35] ; encoding: [0x00,0x00,0x20,0xf0,0xed,0xc1,0x07,0x00]
image_store v193, v[237:240], s[28:35]
// GCN: image_store v193, v[237:240], s[28:35] ; encoding: [0x00,0x00,0x20,0xf0,0xed,0xc1,0x07,0x00]
@ -143,6 +161,15 @@ image_load v[5:7], v[1:4], s[8:15] dmask:0xf tfe d16
// Image Load/Store: PCK variants
//===----------------------------------------------------------------------===//
image_load_mip_pck v5, v1, s[8:15] dmask:0x1
// GCN: image_load_mip_pck v5, v1, s[8:15] dmask:0x1 ; encoding: [0x00,0x01,0x10,0xf0,0x01,0x05,0x02,0x00]
image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1
// GCN: image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 ; encoding: [0x00,0x01,0x10,0xf0,0x01,0x05,0x02,0x00]
image_load_mip_pck v5, v[1:3], s[8:15] dmask:0x1
// GCN: image_load_mip_pck v5, v[1:3], s[8:15] dmask:0x1 ; encoding: [0x00,0x01,0x10,0xf0,0x01,0x05,0x02,0x00]
image_load_mip_pck v5, v[1:4], s[8:15] dmask:0x1
// GCN: image_load_mip_pck v5, v[1:4], s[8:15] dmask:0x1 ; encoding: [0x00,0x01,0x10,0xf0,0x01,0x05,0x02,0x00]
@ -166,6 +193,15 @@ image_load_mip_pck v5, v[1:4], s[8:15] dmask:0x1 d16
// NOVI: error: invalid operand for instruction
// NOGFX9: error: invalid operand for instruction
image_store_mip_pck v252, v2, s[12:19] dmask:0x1 unorm
// GCN: image_store_mip_pck v252, v2, s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x2c,0xf0,0x02,0xfc,0x03,0x00]
image_store_mip_pck v252, v[2:3], s[12:19] dmask:0x1 unorm
// GCN: image_store_mip_pck v252, v[2:3], s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x2c,0xf0,0x02,0xfc,0x03,0x00]
image_store_mip_pck v252, v[2:4], s[12:19] dmask:0x1 unorm
// GCN: image_store_mip_pck v252, v[2:4], s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x2c,0xf0,0x02,0xfc,0x03,0x00]
image_store_mip_pck v252, v[2:5], s[12:19] dmask:0x1 unorm
// GCN: image_store_mip_pck v252, v[2:5], s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x2c,0xf0,0x02,0xfc,0x03,0x00]
@ -187,6 +223,15 @@ image_store_mip_pck v252, v[2:5], s[12:19] dmask:0x1 d16
image_sample v[193:195], v[237:240], s[28:35], s[4:7] dmask:0x7 unorm
// GCN: image_sample v[193:195], v[237:240], s[28:35], s[4:7] dmask:0x7 unorm ; encoding: [0x00,0x17,0x80,0xf0,0xed,0xc1,0x27,0x00]
image_sample v193, v237, s[28:35], s[4:7]
// GCN: image_sample v193, v237, s[28:35], s[4:7] ; encoding: [0x00,0x00,0x80,0xf0,0xed,0xc1,0x27,0x00]
image_sample v193, v[237:238], s[28:35], s[4:7]
// GCN: image_sample v193, v[237:238], s[28:35], s[4:7] ; encoding: [0x00,0x00,0x80,0xf0,0xed,0xc1,0x27,0x00]
image_sample v193, v[237:239], s[28:35], s[4:7]
// GCN: image_sample v193, v[237:239], s[28:35], s[4:7] ; encoding: [0x00,0x00,0x80,0xf0,0xed,0xc1,0x27,0x00]
image_sample v193, v[237:240], s[28:35], s[4:7]
// GCN: image_sample v193, v[237:240], s[28:35], s[4:7] ; encoding: [0x00,0x00,0x80,0xf0,0xed,0xc1,0x27,0x00]
@ -226,6 +271,18 @@ image_sample v[193:194], v[237:240], s[28:35], s[4:7] dmask:0x7 d16
// Image Atomics
//===----------------------------------------------------------------------===//
image_atomic_add v4, v192, s[28:35] dmask:0x1 unorm glc
// SICI: image_atomic_add v4, v192, s[28:35] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x44,0xf0,0xc0,0x04,0x07,0x00]
// GFX89: image_atomic_add v4, v192, s[28:35] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x48,0xf0,0xc0,0x04,0x07,0x00]
image_atomic_add v4, v[192:193], s[28:35] dmask:0x1 unorm glc
// SICI: image_atomic_add v4, v[192:193], s[28:35] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x44,0xf0,0xc0,0x04,0x07,0x00]
// GFX89: image_atomic_add v4, v[192:193], s[28:35] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x48,0xf0,0xc0,0x04,0x07,0x00]
image_atomic_add v4, v[192:194], s[28:35] dmask:0x1 unorm glc
// SICI: image_atomic_add v4, v[192:194], s[28:35] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x44,0xf0,0xc0,0x04,0x07,0x00]
// GFX89: image_atomic_add v4, v[192:194], s[28:35] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x48,0xf0,0xc0,0x04,0x07,0x00]
image_atomic_add v4, v[192:195], s[28:35] dmask:0x1 unorm glc
// SICI: image_atomic_add v4, v[192:195], s[28:35] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x44,0xf0,0xc0,0x04,0x07,0x00]
// GFX89: image_atomic_add v4, v[192:195], s[28:35] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x48,0xf0,0xc0,0x04,0x07,0x00]
@ -283,6 +340,12 @@ image_atomic_add v10, v6, s[8:15] dmask:0x1 r128
image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x1
// GCN: image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x1 ; encoding: [0x00,0x01,0x00,0xf1,0x01,0x05,0x62,0x00]
image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1
// GCN: image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 ; encoding: [0x00,0x01,0x00,0xf1,0x01,0x05,0x62,0x00]
image_gather4 v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
// GCN: image_gather4 v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 ; encoding: [0x00,0x01,0x00,0xf1,0x01,0x05,0x62,0x00]
image_gather4 v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
// GCN: image_gather4 v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2 ; encoding: [0x00,0x02,0x00,0xf1,0x01,0x05,0x62,0x00]