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Re-commit "[PowerPC][NFC][MachinePipeliner] Add some regression testcases""
Remove sms-cpy1.ll first while I investigate the problem. llvm-svn: 368318
This commit is contained in:
Jinsong Ji
parent
7c9c0e003e
commit
0e3e0ac472
67
test/CodeGen/PowerPC/sms-phi-1.ll
Normal file
67
test/CodeGen/PowerPC/sms-phi-1.ll
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@ -0,0 +1,67 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
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; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s
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define void @main() local_unnamed_addr #0 {
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; CHECK-LABEL: main:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: .cfi_offset r30, -16
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; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
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; CHECK-NEXT: std 0, 16(1)
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; CHECK-NEXT: stdu 1, -48(1)
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; CHECK-NEXT: bl strtol
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; CHECK-NEXT: nop
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; CHECK-NEXT: mr 30, 3
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; CHECK-NEXT: bl calloc
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; CHECK-NEXT: nop
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; CHECK-NEXT: clrldi 4, 30, 32
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; CHECK-NEXT: li 5, 0
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; CHECK-NEXT: addi 3, 3, -4
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; CHECK-NEXT: mtctr 4
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; CHECK-NEXT: mullw 4, 5, 5
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; CHECK-NEXT: li 6, 1
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; CHECK-NEXT: bdz .LBB0_3
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: stwu 4, 4(3)
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; CHECK-NEXT: mullw 4, 6, 6
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; CHECK-NEXT: addi 5, 6, 1
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; CHECK-NEXT: bdz .LBB0_3
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB0_2: #
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; CHECK-NEXT: stwu 4, 4(3)
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; CHECK-NEXT: mullw 4, 5, 5
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; CHECK-NEXT: addi 5, 5, 1
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; CHECK-NEXT: bdnz .LBB0_2
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; CHECK-NEXT: .LBB0_3:
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; CHECK-NEXT: stwu 4, 4(3)
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; CHECK-NEXT: addi 1, 1, 48
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; CHECK-NEXT: ld 0, 16(1)
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; CHECK-NEXT: mtlr 0
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; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload
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; CHECK-NEXT: blr
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%1 = tail call i64 @strtol()
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%2 = trunc i64 %1 to i32
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%3 = tail call noalias i8* @calloc()
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%4 = bitcast i8* %3 to i32*
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%5 = zext i32 %2 to i64
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br label %6
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6: ; preds = %6, %0
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%7 = phi i64 [ %11, %6 ], [ 0, %0 ]
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%8 = trunc i64 %7 to i32
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%9 = mul nsw i32 %8, %8
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%10 = getelementptr inbounds i32, i32* %4, i64 %7
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store i32 %9, i32* %10, align 4
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%11 = add nuw nsw i64 %7, 1
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%12 = icmp eq i64 %11, %5
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br i1 %12, label %13, label %6
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13: ; preds = %6
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ret void
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}
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declare i8* @calloc() local_unnamed_addr
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declare i64 @strtol() local_unnamed_addr
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69
test/CodeGen/PowerPC/sms-phi-2.ll
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69
test/CodeGen/PowerPC/sms-phi-2.ll
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@ -0,0 +1,69 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
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; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s
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define void @phi2(i32, i32, i8*) local_unnamed_addr {
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; CHECK-LABEL: phi2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: divw 8, 3, 4
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; CHECK-NEXT: li 5, 55
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; CHECK-NEXT: li 6, 48
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; CHECK-NEXT: mtctr 3
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; CHECK-NEXT: bdz .LBB0_4
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: divw 9, 8, 4
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; CHECK-NEXT: mullw 7, 8, 4
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; CHECK-NEXT: subf 3, 7, 3
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; CHECK-NEXT: cmplwi 3, 10
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; CHECK-NEXT: isel 7, 6, 5, 0
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; CHECK-NEXT: add 3, 7, 3
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; CHECK-NEXT: stbu 3, -1(7)
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; CHECK-NEXT: mr 3, 8
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; CHECK-NEXT: bdz .LBB0_3
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB0_2: #
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; CHECK-NEXT: mr 3, 9
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; CHECK-NEXT: mullw 9, 9, 4
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; CHECK-NEXT: divw 10, 3, 4
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; CHECK-NEXT: subf 8, 9, 8
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; CHECK-NEXT: cmplwi 8, 10
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; CHECK-NEXT: isel 9, 6, 5, 0
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; CHECK-NEXT: add 8, 9, 8
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; CHECK-NEXT: mr 9, 10
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; CHECK-NEXT: stbu 8, -1(7)
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; CHECK-NEXT: mr 8, 3
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; CHECK-NEXT: bdnz .LBB0_2
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; CHECK-NEXT: .LBB0_3:
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; CHECK-NEXT: mr 8, 9
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; CHECK-NEXT: b .LBB0_5
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; CHECK-NEXT: .LBB0_4:
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; CHECK-NEXT: # implicit-def: $x7
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; CHECK-NEXT: .LBB0_5:
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; CHECK-NEXT: mullw 4, 8, 4
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; CHECK-NEXT: subf 3, 4, 3
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; CHECK-NEXT: cmplwi 3, 10
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; CHECK-NEXT: isel 4, 6, 5, 0
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; CHECK-NEXT: add 3, 4, 3
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; CHECK-NEXT: stbu 3, -1(7)
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; CHECK-NEXT: blr
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br label %4
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4: ; preds = %4, %3
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%5 = phi i64 [ %7, %4 ], [ undef, %3 ]
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%6 = phi i32 [ %8, %4 ], [ %0, %3 ]
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%7 = add nsw i64 %5, -1
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%8 = sdiv i32 %6, %1
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%9 = mul nsw i32 %8, %1
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%10 = sub nsw i32 %6, %9
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%11 = icmp ult i32 %10, 10
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%12 = trunc i32 %10 to i8
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%13 = select i1 %11, i8 48, i8 55
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%14 = add i8 %13, %12
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%15 = getelementptr inbounds i8, i8* %2, i64 %7
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store i8 %14, i8* %15, align 1
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%16 = icmp sgt i64 %5, 1
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br i1 %16, label %4, label %17
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17: ; preds = %4
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ret void
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}
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89
test/CodeGen/PowerPC/sms-phi-3.ll
Normal file
89
test/CodeGen/PowerPC/sms-phi-3.ll
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@ -0,0 +1,89 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
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; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s
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%0 = type { double, double, double, i32, i32 }
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declare i8* @malloc() local_unnamed_addr
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define void @phi3(i32*) local_unnamed_addr {
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; CHECK-LABEL: phi3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: .cfi_def_cfa_offset 64
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: .cfi_offset r29, -24
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; CHECK-NEXT: .cfi_offset r30, -16
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; CHECK-NEXT: std 29, -24(1) # 8-byte Folded Spill
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; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
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; CHECK-NEXT: std 0, 16(1)
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; CHECK-NEXT: stdu 1, -64(1)
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; CHECK-NEXT: mr 30, 3
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; CHECK-NEXT: bl malloc
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; CHECK-NEXT: nop
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; CHECK-NEXT: mr 29, 3
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; CHECK-NEXT: bl malloc
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi 7, 30, -4
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; CHECK-NEXT: mtctr 3
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; CHECK-NEXT: lwzu 8, 4(7)
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; CHECK-NEXT: addi 4, 29, -8
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; CHECK-NEXT: li 5, 0
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; CHECK-NEXT: bdz .LBB0_5
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: extswsli 6, 5, 5
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; CHECK-NEXT: add 5, 8, 5
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; CHECK-NEXT: lwzu 8, 4(7)
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; CHECK-NEXT: bdz .LBB0_4
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; CHECK-NEXT: # %bb.2:
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; CHECK-NEXT: add 6, 3, 6
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; CHECK-NEXT: stdu 6, 8(4)
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; CHECK-NEXT: extswsli 6, 5, 5
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; CHECK-NEXT: add 5, 8, 5
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; CHECK-NEXT: lwzu 8, 4(7)
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; CHECK-NEXT: bdz .LBB0_4
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; CHECK-NEXT: .p2align 5
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; CHECK-NEXT: .LBB0_3: #
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; CHECK-NEXT: add 9, 3, 6
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; CHECK-NEXT: extswsli 6, 5, 5
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; CHECK-NEXT: add 5, 8, 5
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; CHECK-NEXT: lwzu 8, 4(7)
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; CHECK-NEXT: stdu 9, 8(4)
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; CHECK-NEXT: bdnz .LBB0_3
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; CHECK-NEXT: .LBB0_4:
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; CHECK-NEXT: add 6, 3, 6
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; CHECK-NEXT: stdu 6, 8(4)
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; CHECK-NEXT: .LBB0_5:
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; CHECK-NEXT: extswsli 5, 5, 5
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; CHECK-NEXT: add 3, 3, 5
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; CHECK-NEXT: stdu 3, 8(4)
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; CHECK-NEXT: addi 1, 1, 64
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; CHECK-NEXT: ld 0, 16(1)
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; CHECK-NEXT: mtlr 0
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; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload
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; CHECK-NEXT: ld 29, -24(1) # 8-byte Folded Reload
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; CHECK-NEXT: blr
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%2 = tail call noalias i8* @malloc()
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%3 = bitcast i8* %2 to %0**
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%4 = tail call noalias i8* @malloc()
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%5 = bitcast i8* %4 to %0*
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br label %6
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6: ; preds = %6, %1
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%7 = phi i64 [ %16, %6 ], [ 0, %1 ]
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%8 = phi i32 [ %15, %6 ], [ 0, %1 ]
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%9 = phi i64 [ %17, %6 ], [ undef, %1 ]
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%10 = sext i32 %8 to i64
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%11 = getelementptr inbounds %0, %0* %5, i64 %10
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%12 = getelementptr inbounds %0*, %0** %3, i64 %7
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store %0* %11, %0** %12, align 8
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%13 = getelementptr inbounds i32, i32* %0, i64 %7
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%14 = load i32, i32* %13, align 4
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%15 = add nsw i32 %14, %8
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%16 = add nuw nsw i64 %7, 1
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%17 = add i64 %9, -1
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%18 = icmp eq i64 %17, 0
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br i1 %18, label %19, label %6
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19: ; preds = %6
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ret void
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}
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56
test/CodeGen/PowerPC/sms-phi-5.ll
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56
test/CodeGen/PowerPC/sms-phi-5.ll
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@ -0,0 +1,56 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
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; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s
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define void @phi5() unnamed_addr {
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; CHECK-LABEL: phi5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: slw 3, 4, 3
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; CHECK-NEXT: andi. 3, 3, 6336
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; CHECK-NEXT: beqlr 0
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; CHECK-NEXT: # %bb.2:
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; CHECK-NEXT: lhz 3, 0(3)
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; CHECK-NEXT: slwi 3, 3, 15
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; CHECK-NEXT: clrlwi 3, 3, 31
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; CHECK-NEXT: rlwinm 4, 3, 31, 17, 31
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: rlwimi 3, 3, 15, 0, 16
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; CHECK-NEXT: # %bb.3:
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; CHECK-NEXT: blr
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switch i12 undef, label %21 [
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i12 6, label %1
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i12 7, label %1
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i12 12, label %1
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i12 11, label %1
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]
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1: ; preds = %0, %0, %0, %0
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%2 = load i16, i16* undef, align 2
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br label %3
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3: ; preds = %3, %1
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%4 = phi i16 [ %18, %3 ], [ undef, %1 ]
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%5 = phi i16 [ %13, %3 ], [ undef, %1 ]
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%6 = phi i16 [ %11, %3 ], [ undef, %1 ]
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%7 = phi i16 [ undef, %3 ], [ %2, %1 ]
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%8 = phi i32 [ %19, %3 ], [ undef, %1 ]
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%9 = lshr i16 %6, 1
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%10 = shl i16 %7, 15
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%11 = or i16 %10, %9
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%12 = shl i16 %6, 15
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%13 = or i16 %12, 0
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%14 = and i16 %4, 1
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%15 = lshr i16 %4, 1
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%16 = shl i16 %5, 15
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%17 = or i16 %14, %15
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%18 = or i16 %17, %16
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%19 = add i32 %8, -1
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%20 = icmp eq i32 %19, 0
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br i1 %20, label %21, label %3
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21: ; preds = %3, %0
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ret void
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}
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