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Correctly handle <undef> tied uses when rewriting after a split.
This fixes PR10463. A two-address instruction with an <undef> use operand was incorrectly rewritten so the def and use no longer used the same register, violating the tie constraint. Fix this by always rewriting <undef> operands with the register a def operand would use. llvm-svn: 135885
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@ -938,15 +938,11 @@ void SplitEditor::rewriteAssigned(bool ExtendRanges) {
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continue;
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}
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// <undef> operands don't really read the register, so just assign them to
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// the complement.
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if (MO.isUse() && MO.isUndef()) {
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MO.setReg(Edit->get(0)->reg);
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continue;
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}
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// <undef> operands don't really read the register, so it doesn't matter
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// which register we choose. When the use operand is tied to a def, we must
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// use the same register as the def, so just do that always.
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SlotIndex Idx = LIS.getInstructionIndex(MI);
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if (MO.isDef())
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if (MO.isDef() || MO.isUndef())
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Idx = MO.isEarlyClobber() ? Idx.getUseIndex() : Idx.getDefIndex();
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// Rewrite to the mapped register at Idx.
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@ -316,3 +316,28 @@ declare void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_c
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declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind
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declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind
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; PR10463
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; Spilling a virtual register with <undef> uses.
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define void @autogen_239_1000() {
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BB:
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%Shuff = shufflevector <8 x double> undef, <8 x double> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 undef, i32 undef>
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br label %CF
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CF:
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%B16 = frem <8 x double> zeroinitializer, %Shuff
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%E19 = extractelement <8 x double> %Shuff, i32 5
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br i1 undef, label %CF, label %CF75
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CF75:
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br i1 undef, label %CF75, label %CF76
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CF76:
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store double %E19, double* undef
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br i1 undef, label %CF76, label %CF77
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CF77:
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%B55 = fmul <8 x double> %B16, undef
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br label %CF77
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}
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