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[PPC] Fix the scheduling of CR logicals on the P7

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CR logicals (crand, crxor, etc.) on the P7 need to be in the first slot of each
dispatch group. The old itinerary entry was just wrong (but has not mattered
because we don't generate these instructions).

This will matter when, in an upcoming commit, we start generating these
instructions.

llvm-svn: 198359
This commit is contained in:
Hal Finkel 2014-01-02 21:38:26 +00:00
parent 16caa8023c
commit 0e77f939b4
2 changed files with 3 additions and 2 deletions
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1
lib/Target/PowerPC/PPCHazardRecognizers.cpp
View File

@ -128,6 +128,7 @@ bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID,
default: default:
// All multi-slot instructions must come first. // All multi-slot instructions must come first.
return NSlots > 1; return NSlots > 1;
case PPC::Sched::IIC_BrCR: // cr logicals
case PPC::Sched::IIC_SprMFCR: case PPC::Sched::IIC_SprMFCR:
case PPC::Sched::IIC_SprMFCRF: case PPC::Sched::IIC_SprMFCRF:
case PPC::Sched::IIC_SprMTSPR: case PPC::Sched::IIC_SprMTSPR:

4
lib/Target/PowerPC/PPCScheduleP7.td
View File

@ -137,8 +137,8 @@ def P7Itineraries : ProcessorItineraries<
InstrItinData<IIC_BrB , [InstrStage<1, [P7_DU5, P7_DU6], 0>, InstrItinData<IIC_BrB , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
InstrStage<1, [P7_BRU]>], InstrStage<1, [P7_BRU]>],
[3, 1, 1]>, [3, 1, 1]>,
InstrItinData<IIC_BrCR , [InstrStage<1, [P7_DU5, P7_DU6], 0>, InstrItinData<IIC_BrCR , [InstrStage<1, [P7_DU1], 0>,
InstrStage<1, [P7_BRU]>], InstrStage<1, [P7_CRU]>],
[3, 1, 1]>, [3, 1, 1]>,
InstrItinData<IIC_BrMCR , [InstrStage<1, [P7_DU5, P7_DU6], 0>, InstrItinData<IIC_BrMCR , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
InstrStage<1, [P7_BRU]>], InstrStage<1, [P7_BRU]>],