RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 20:23:11 +01:00
Code Issues Projects Releases Wiki Activity

[Support] Add KnownBits::sextInReg exhaustive tests

Browse Source 
Requested by @foad in rG9cf4f493a72f
This commit is contained in:
Simon Pilgrim 2021-01-14 14:18:55 +00:00
parent 817ed0fdbd
commit 0e8dbbda98
1 changed files with 20 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
unittests/Support/KnownBitsTest.cpp
View File

@ -425,4 +425,24 @@ TEST(KnownBitsTest, SExtOrTrunc) {
}
}
TEST(KnownBitsTest, SExtInReg) {
unsigned Bits = 4;
for (unsigned FromBits = 1; FromBits != Bits; ++FromBits) {
ForeachKnownBits(Bits, [&](const KnownBits &Known) {
APInt CommonOne = APInt::getAllOnesValue(Bits);
APInt CommonZero = APInt::getAllOnesValue(Bits);
unsigned ExtBits = Bits - FromBits;
ForeachNumInKnownBits(Known, [&](const APInt &N) {
APInt Ext = N << ExtBits;
Ext.ashrInPlace(ExtBits);
CommonOne &= Ext;
CommonZero &= ~Ext;
});
KnownBits KnownSExtInReg = Known.sextInReg(FromBits);
EXPECT_EQ(CommonOne, KnownSExtInReg.One);
EXPECT_EQ(CommonZero, KnownSExtInReg.Zero);
});
}
}
} // end anonymous namespace