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Add ability to emit internal instruction representation to CodeGen assembly output.
Summary: This patch re-uses the implementation of 'llvm-mc -show-inst' and makes it available to llc as 'llc -asm-show-inst'. This is necessary to test parts of MIPS32r6/MIPS64r6 without resorting to 'llc -filetype=obj' tests. For example, on MIPS32r2 and earlier we use the 'jr $rs' instruction for indirect branches and returns. On MIPS32r6, we no longer have 'jr $rs' and use 'jalr $zero, $rs' instead. The catch is that, on MIPS32r6, 'jr $rs' is an alias for 'jalr $zero, $rs' and is the preferred way of writing this instruction. As a result, all MIPS ISA's emit 'jr $rs' in their assembly output and the assembler encodes this to different opcodes according to the ISA. Using this option, we can check that the MCInst really is a JR or a JALR by matching the emitted comment. This removes the need for a 'llc -filetype=obj' test. Reviewers: rafael, dsanders Reviewed By: dsanders Subscribers: zoran.jovanovic, llvm-commits Differential Revision: http://reviews.llvm.org/D4267 llvm-svn: 212603
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@ -36,12 +36,17 @@ cl::opt<bool> RelaxAll("mc-relax-all",
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cl::opt<int> DwarfVersion("dwarf-version", cl::desc("Dwarf version"),
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cl::init(0));
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cl::opt<bool> ShowMCInst("asm-show-inst",
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cl::desc("Emit internal instruction representation to "
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"assembly file"));
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static inline MCTargetOptions InitMCTargetOptionsFromFlags() {
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MCTargetOptions Options;
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Options.SanitizeAddress =
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(AsmInstrumentation == MCTargetOptions::AsmInstrumentationAddress);
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Options.MCRelaxAll = RelaxAll;
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Options.DwarfVersion = DwarfVersion;
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Options.ShowMCInst = ShowMCInst;
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return Options;
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}
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