From 0ec2cb142d31c2cafcdc0b5e86a7bc03472a952f Mon Sep 17 00:00:00 2001 From: Li Jia He Date: Thu, 1 Nov 2018 02:35:17 +0000 Subject: [PATCH] =?UTF-8?q?[PowerPC]=20Support=20constraint=20'wi'=20in=20?= =?UTF-8?q?asm=20=20=20From=20the=20gcc=20manual,=20we=20can=20see=20that?= =?UTF-8?q?=20the=20specific=20limit=20of=20wi=20inline=20asm=20is=20?= =?UTF-8?q?=E2=80=9CFP=20or=20VSX=20register=20to=20hold=2064-bit=20intege?= =?UTF-8?q?rs=20for=20VSX=20insns=20or=20NO=5FREGS=E2=80=9D.=20The=20link?= =?UTF-8?q?=20is=C2=A0https://gcc.gnu.org/onlinedocs/gcc-8.2.0/gcc/Machine?= =?UTF-8?q?-Constraints.html#Machine-Constraints.=C2=A0We=20should=20accep?= =?UTF-8?q?t=20this=20constraint.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D53265 llvm-svn: 345810 --- lib/Target/PowerPC/PPCISelLowering.cpp | 8 ++++++-- test/CodeGen/PowerPC/inlineasm-vsx-reg.ll | 15 +++++++++++++++ test/CodeGen/PowerPC/vec-asm-disabled.ll | 9 +++++++++ 3 files changed, 30 insertions(+), 2 deletions(-) diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index a135667beaa..4ed110e6663 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -13362,7 +13362,8 @@ PPCTargetLowering::getConstraintType(StringRef Constraint) const { } else if (Constraint == "wc") { // individual CR bits. return C_RegisterClass; } else if (Constraint == "wa" || Constraint == "wd" || - Constraint == "wf" || Constraint == "ws") { + Constraint == "wf" || Constraint == "ws" || + Constraint == "wi") { return C_RegisterClass; // VSX registers. } return TargetLowering::getConstraintType(Constraint); @@ -13392,6 +13393,8 @@ PPCTargetLowering::getSingleConstraintMatchWeight( return CW_Register; else if (StringRef(constraint) == "ws" && type->isDoubleTy()) return CW_Register; + else if (StringRef(constraint) == "wi" && type->isIntegerTy(64)) + return CW_Register; // just hold 64-bit integers data. switch (*constraint) { default: @@ -13474,7 +13477,8 @@ PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, // An individual CR bit. return std::make_pair(0U, &PPC::CRBITRCRegClass); } else if ((Constraint == "wa" || Constraint == "wd" || - Constraint == "wf") && Subtarget.hasVSX()) { + Constraint == "wf" || Constraint == "wi") && + Subtarget.hasVSX()) { return std::make_pair(0U, &PPC::VSRCRegClass); } else if (Constraint == "ws" && Subtarget.hasVSX()) { if (VT == MVT::f32 && Subtarget.hasP8Vector()) diff --git a/test/CodeGen/PowerPC/inlineasm-vsx-reg.ll b/test/CodeGen/PowerPC/inlineasm-vsx-reg.ll index 9de6358427d..0ebb4493065 100644 --- a/test/CodeGen/PowerPC/inlineasm-vsx-reg.ll +++ b/test/CodeGen/PowerPC/inlineasm-vsx-reg.ll @@ -12,6 +12,21 @@ entry: ; CHECK: #NO_APP } +define signext i32 @foo1(<4 x float> %__A) { +entry: + %0 = tail call { i32, <4 x float> } asm "xxsldwi ${1:x},${2:x},${2:x},3;\0Axscvspdp ${1:x},${1:x};\0Afctiw $1,$1;\0Amfvsrd $0,${1:x};\0A", "=r,=&^wi,^wa"(<4 x float> %__A) + %asmresult = extractvalue { i32, <4 x float> } %0, 0 + ret i32 %asmresult + +; CHECK: #APP +; CHECK: xxsldwi vs0, v2, v2, 3 +; CHECK: xscvspdp f0, f0 +; CEHCK: fctiw f0, f0 +; CHECK: mffprd r3, f0 +; CEHCK: extsw r3, r3 +; CHECK: #NO_APP +} + define double @test() { entry: %0 = tail call double asm "mtvsrd ${0:x}, 1", "=^ws,~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14}"() diff --git a/test/CodeGen/PowerPC/vec-asm-disabled.ll b/test/CodeGen/PowerPC/vec-asm-disabled.ll index 333ccce6b89..614f3e3f03a 100644 --- a/test/CodeGen/PowerPC/vec-asm-disabled.ll +++ b/test/CodeGen/PowerPC/vec-asm-disabled.ll @@ -10,5 +10,14 @@ entry: ; CHECK: error: couldn't allocate output register for constraint 'wd' } +define signext i32 @testi2(<4 x float> %__A) #0 { +entry: + %0 = tail call { i32, <4 x float> } asm "xxsldwi ${1:x},${2:x},${2:x},3", "=^wi,=&^wi,^wi"(<4 x float> %__A) #0 + %asmresult = extractvalue { i32, <4 x float> } %0, 0 + ret i32 %asmresult + +; CHECK: error: couldn't allocate output register for constraint 'wi' +} + attributes #0 = { nounwind "target-features"="-vsx" }