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Don't print (PLT) on arm.

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The R_ARM_PLT32 relocation is deprecated and is not produced by MC.

This means that the code being deleted is dead from the .o point of
view and was making the .s more confusing.

llvm-svn: 272909
This commit is contained in:
Rafael Espindola 2016-06-16 16:09:53 +00:00
parent b66ccf69d1
commit 0ed05f79e1
10 changed files with 29 additions and 57 deletions
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2
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -212,8 +212,6 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
GetARMGVSymbol(GV, TF)->print(O, MAI);
printOffset(MO.getOffset(), O);
if (TF == ARMII::MO_PLT)
O << "(PLT)";
break;
}
case MachineOperand::MO_ConstantPoolIndex:

11
lib/Target/ARM/ARMFastISel.cpp
View File

@ -2430,22 +2430,15 @@ bool ARMFastISel::SelectCall(const Instruction *I,
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
DbgLoc, TII.get(CallOpc));
unsigned char OpFlags = 0;
// Add MO_PLT for global address or external symbol in the PIC relocation
// model.
if (Subtarget->isTargetELF() && TM.getRelocationModel() == Reloc::PIC_)
OpFlags = ARMII::MO_PLT;
// ARM calls don't take a predicate, but tBL / tBLX do.
if(isThumb2)
AddDefaultPred(MIB);
if (UseReg)
MIB.addReg(CalleeReg);
else if (!IntrMemName)
MIB.addGlobalAddress(GV, 0, OpFlags);
MIB.addGlobalAddress(GV, 0, 0);
else
MIB.addExternalSymbol(IntrMemName, OpFlags);
MIB.addExternalSymbol(IntrMemName, 0);
// Add implicit physical register uses to the call.
for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)

14
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -1878,12 +1878,7 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
MachinePointerInfo::getGOT(DAG.getMachineFunction()),
false, false, false, 0);
} else {
// On ELF targets for PIC code, direct calls should go through the PLT
unsigned OpFlags = 0;
if (Subtarget->isTargetELF() &&
getTargetMachine().getRelocationModel() == Reloc::PIC_)
OpFlags = ARMII::MO_PLT;
Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, OpFlags);
Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
}
} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
isDirect = true;
@ -1903,12 +1898,7 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
} else {
unsigned OpFlags = 0;
// On ELF targets for PIC code, direct calls should go through the PLT
if (Subtarget->isTargetELF() &&
getTargetMachine().getRelocationModel() == Reloc::PIC_)
OpFlags = ARMII::MO_PLT;
Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, OpFlags);
Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
}
}

5
lib/Target/ARM/ARMMCInstLower.cpp
View File

@ -49,11 +49,6 @@ MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO,
}
break;
}
case ARMII::MO_PLT:
Expr = MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_PLT,
OutContext);
break;
}
if (!MO.isJTI() && MO.getOffset())

4
lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
View File

@ -289,10 +289,6 @@ namespace ARMII {
/// higher 16 bit of the address. Used only via movt instruction.
MO_HI16 = 0x2,
/// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
/// call operand.
MO_PLT = 0x3,
/// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects
/// just that part of the flag set.
MO_OPTION_MASK = 0x1f,

10
test/CodeGen/ARM/call-tc.ll
View File

@ -12,7 +12,7 @@ declare void @g(i32, i32, i32, i32)
define void @t1() {
; CHECKELF-LABEL: t1:
; CHECKELF: bl g(PLT)
; CHECKELF: bl g
call void @g( i32 1, i32 2, i32 3, i32 4 )
ret void
}
@ -33,7 +33,7 @@ define void @t3() {
; CHECKV6-LABEL: t3:
; CHECKV6: b _t2
; CHECKELF-LABEL: t3:
; CHECKELF: b t2(PLT)
; CHECKELF: b t2
; CHECKT2D-LABEL: t3:
; CHECKT2D: b.w _t2
@ -47,7 +47,7 @@ entry:
; CHECKV6-LABEL: t4:
; CHECKV6: b _sin
; CHECKELF-LABEL: t4:
; CHECKELF: b sin(PLT)
; CHECKELF: b sin
%0 = tail call double @sin(double %a) nounwind readonly ; <double> [#uses=1]
ret double %0
}
@ -57,7 +57,7 @@ entry:
; CHECKV6-LABEL: t5:
; CHECKV6: b _sinf
; CHECKELF-LABEL: t5:
; CHECKELF: b sinf(PLT)
; CHECKELF: b sinf
%0 = tail call float @sinf(float %a) nounwind readonly ; <float> [#uses=1]
ret float %0
}
@ -71,7 +71,7 @@ entry:
; CHECKV6-LABEL: t6:
; CHECKV6: b ___divsi3
; CHECKELF-LABEL: t6:
; CHECKELF: b __aeabi_idiv(PLT)
; CHECKELF: b __aeabi_idiv
%0 = sdiv i32 %a, %b
ret i32 %0
}

2
test/CodeGen/ARM/call.ll
View File

@ -12,7 +12,7 @@
declare void @g(i32, i32, i32, i32)
define void @f() {
; CHECKELF: PLT
; CHECKELF: bl g
call void @g( i32 1, i32 2, i32 3, i32 4 )
ret void
}

30
test/CodeGen/ARM/emutls.ll
View File

@ -11,7 +11,7 @@ define i32 @my_get_xyz() {
; ARM32-LABEL: my_get_xyz:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
; ARM32-NEXT: bl my_emutls_get_address(PLT)
; ARM32-NEXT: bl my_emutls_get_address
; ARM32-NEXT: ldr r0, [r0]
; ARM32: .long my_emutls_v_xyz(GOT_PREL)
@ -34,7 +34,7 @@ define i32 @f1() {
; ARM32-LABEL: f1:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
; ARM32-NEXT: bl __emutls_get_address(PLT)
; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldr r0, [r0]
; ARM32: .long __emutls_v.i1(GOT_PREL)
@ -47,7 +47,7 @@ define i32* @f2() {
; ARM32-LABEL: f2:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
; ARM32-NEXT: bl __emutls_get_address(PLT)
; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: pop
; ARM32: .long __emutls_v.i1(GOT_PREL)
@ -59,7 +59,7 @@ define i32 @f3() nounwind {
; ARM32-LABEL: f3:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
; ARM32-NEXT: bl __emutls_get_address(PLT)
; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldr r0, [r0]
; ARM32: .long __emutls_v.i2(GOT_PREL)
@ -72,7 +72,7 @@ define i32* @f4() {
; ARM32-LABEL: f4:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
; ARM32-NEXT: bl __emutls_get_address(PLT)
; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: pop
; ARM32: .long __emutls_v.i2(GOT_PREL)
@ -84,7 +84,7 @@ define i32 @f5() nounwind {
; ARM32-LABEL: f5:
; ARM32: ldr r0,
; ARM32: add r0, pc, r0
; ARM32-NEXT: bl __emutls_get_address(PLT)
; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldr r0, [r0]
; ARM32: .long __emutls_v.i3-
@ -97,7 +97,7 @@ define i32* @f6() {
; ARM32-LABEL: f6:
; ARM32: ldr r0,
; ARM32: add r0, pc, r0
; ARM32-NEXT: bl __emutls_get_address(PLT)
; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: pop
; ARM32: .long __emutls_v.i3-
@ -109,7 +109,7 @@ define i32 @f7() {
; ARM32-LABEL: f7:
; ARM32: ldr r0,
; ARM32: add r0, pc, r0
; ARM32-NEXT: bl __emutls_get_address(PLT)
; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldr r0, [r0]
; ARM32: .long __emutls_v.i4-(.LPC
@ -122,7 +122,7 @@ define i32* @f8() {
; ARM32-LABEL: f8:
; ARM32: ldr r0,
; ARM32: add r0, pc, r0
; ARM32-NEXT: bl __emutls_get_address(PLT)
; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: pop
; ARM32: .long __emutls_v.i4-(.LPC
@ -134,7 +134,7 @@ define i32 @f9() {
; ARM32-LABEL: f9:
; ARM32: ldr r0,
; ARM32: add r0, pc, r0
; ARM32-NEXT: bl __emutls_get_address(PLT)
; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldr r0, [r0]
entry:
@ -146,7 +146,7 @@ define i32* @f10() {
; ARM32-LABEL: f10:
; ARM32: ldr r0,
; ARM32: add r0, pc, r0
; ARM32-NEXT: bl __emutls_get_address(PLT)
; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: pop
entry:
@ -157,7 +157,7 @@ define i16 @f11() {
; ARM32-LABEL: f11:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
; ARM32-NEXT: bl __emutls_get_address(PLT)
; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldrh r0, [r0]
entry:
@ -169,7 +169,7 @@ define i32 @f12() {
; ARM32-LABEL: f12:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
; ARM32-NEXT: bl __emutls_get_address(PLT)
; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldrsh r0, [r0]
entry:
@ -182,7 +182,7 @@ define i8 @f13() {
; ARM32-LABEL: f13:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
; ARM32-NEXT: bl __emutls_get_address(PLT)
; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldrb r0, [r0]
; ARM32-NEXT: pop
@ -195,7 +195,7 @@ define i32 @f14() {
; ARM32-LABEL: f14:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
; ARM32-NEXT: bl __emutls_get_address(PLT)
; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldrsb r0, [r0]
; ARM32-NEXT: pop

4
test/CodeGen/ARM/pic.ll
View File

@ -11,10 +11,10 @@ define void @test() {
entry:
%0 = call i32 @get()
; CHECK: bl get(PLT)
; CHECK: bl get
call void @put(i32 %0)
; CHECK: bl put(PLT)
; CHECK: bl put
ret void
}

4
test/CodeGen/Thumb2/tls2.ll
View File

@ -11,7 +11,7 @@ entry:
; CHECK-NOT-PIC: i(GOTTPOFF)
; CHECK-PIC-LABEL: f:
; CHECK-PIC: bl __tls_get_addr(PLT)
; CHECK-PIC: bl __tls_get_addr
%tmp1 = load i32, i32* @i ; <i32> [#uses=1]
ret i32 %tmp1
}
@ -24,6 +24,6 @@ entry:
; CHECK-NOT-PIC: i(GOTTPOFF)
; CHECK-PIC-LABEL: g:
; CHECK-PIC: bl __tls_get_addr(PLT)
; CHECK-PIC: bl __tls_get_addr
ret i32* @i
}