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expand tblgen's support for instructions with implicit defs.
llvm-svn: 98900
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@ -1163,12 +1163,14 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
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} else if (!InstInfo.ImplicitDefs.empty()) {
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// If the instruction has implicit defs, the first one defines the result
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// type.
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assert(InstInfo.ImplicitDefs[0]->isSubClassOf("Register"));
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Record *FirstImplicitDef = InstInfo.ImplicitDefs[0];
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assert(FirstImplicitDef->isSubClassOf("Register"));
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const std::vector<MVT::SimpleValueType> &RegVTs =
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CDP.getTargetInfo().getRegisterVTs(FirstImplicitDef);
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if (!RegVTs.empty())
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if (RegVTs.size() == 1)
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ResultType = EEVT::TypeSet(RegVTs);
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else
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ResultType = EEVT::TypeSet(MVT::isVoid, TP);
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} else {
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// Otherwise, the instruction produces no value result.
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// FIXME: Model "no result" different than "one result that is void"
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@ -698,7 +698,7 @@ EmitResultInstructionAsOperand(const TreePatternNode *N,
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// occur in patterns like (mul:i8 AL:i8, GR8:i8:$src).
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for (unsigned i = 0, e = PhysRegInputs.size(); i != e; ++i)
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AddMatcher(new EmitCopyToRegMatcher(PhysRegInputs[i].second,
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PhysRegInputs[i].first));
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PhysRegInputs[i].first));
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// Even if the node has no other flag inputs, the resultant node must be
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// flagged to the CopyFromReg nodes we just generated.
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TreeHasInFlag = true;
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@ -708,12 +708,11 @@ EmitResultInstructionAsOperand(const TreePatternNode *N,
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// Determine the result types.
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SmallVector<MVT::SimpleValueType, 4> ResultVTs;
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if (NumResults != 0 && N->getType() != MVT::isVoid) {
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if (N->getType() != MVT::isVoid) {
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// FIXME2: If the node has multiple results, we should add them. For now,
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// preserve existing behavior?!
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ResultVTs.push_back(N->getType());
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}
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// If this is the root instruction of a pattern that has physical registers in
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// its result pattern, add output VTs for them. For example, X86 has:
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@ -721,9 +720,18 @@ EmitResultInstructionAsOperand(const TreePatternNode *N,
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// This also handles implicit results like:
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// (implicit EFLAGS)
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if (isRoot && Pattern.getDstRegs().size() != 0) {
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for (unsigned i = 0; i != Pattern.getDstRegs().size(); ++i)
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if (Pattern.getDstRegs()[i]->isSubClassOf("Register"))
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ResultVTs.push_back(getRegisterValueType(Pattern.getDstRegs()[i], CGT));
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// If the root came from an implicit def in the instruction handling stuff,
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// don't re-add it.
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Record *HandledReg = 0;
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if (NumResults == 0 && N->getType() != MVT::isVoid &&
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!II.ImplicitDefs.empty())
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HandledReg = II.ImplicitDefs[0];
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for (unsigned i = 0; i != Pattern.getDstRegs().size(); ++i) {
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Record *Reg = Pattern.getDstRegs()[i];
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if (!Reg->isSubClassOf("Register") || Reg == HandledReg) continue;
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ResultVTs.push_back(getRegisterValueType(Reg, CGT));
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}
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}
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// FIXME2: Instead of using the isVariadic flag on the instruction, we should
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