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expand tblgen's support for instructions with implicit defs.

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llvm-svn: 98900
This commit is contained in:
Chris Lattner 2010-03-18 23:57:40 +00:00
parent 5becdf478d
commit 0ed7a372d6
2 changed files with 18 additions and 8 deletions
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6
utils/TableGen/CodeGenDAGPatterns.cpp
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@ -1163,12 +1163,14 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
} else if (!InstInfo.ImplicitDefs.empty()) {
// If the instruction has implicit defs, the first one defines the result
// type.
assert(InstInfo.ImplicitDefs[0]->isSubClassOf("Register"));
Record *FirstImplicitDef = InstInfo.ImplicitDefs[0];
assert(FirstImplicitDef->isSubClassOf("Register"));
const std::vector<MVT::SimpleValueType> &RegVTs =
CDP.getTargetInfo().getRegisterVTs(FirstImplicitDef);
if (!RegVTs.empty())
if (RegVTs.size() == 1)
ResultType = EEVT::TypeSet(RegVTs);
else
ResultType = EEVT::TypeSet(MVT::isVoid, TP);
} else {
// Otherwise, the instruction produces no value result.
// FIXME: Model "no result" different than "one result that is void"

18
utils/TableGen/DAGISelMatcherGen.cpp
View File

@ -708,22 +708,30 @@ EmitResultInstructionAsOperand(const TreePatternNode *N,
// Determine the result types.
SmallVector<MVT::SimpleValueType, 4> ResultVTs;
if (NumResults != 0 && N->getType() != MVT::isVoid) {
if (N->getType() != MVT::isVoid) {
// FIXME2: If the node has multiple results, we should add them. For now,
// preserve existing behavior?!
ResultVTs.push_back(N->getType());
}
// If this is the root instruction of a pattern that has physical registers in
// its result pattern, add output VTs for them. For example, X86 has:
// (set AL, (mul ...))
// This also handles implicit results like:
// (implicit EFLAGS)
if (isRoot && Pattern.getDstRegs().size() != 0) {
for (unsigned i = 0; i != Pattern.getDstRegs().size(); ++i)
if (Pattern.getDstRegs()[i]->isSubClassOf("Register"))
ResultVTs.push_back(getRegisterValueType(Pattern.getDstRegs()[i], CGT));
// If the root came from an implicit def in the instruction handling stuff,
// don't re-add it.
Record *HandledReg = 0;
if (NumResults == 0 && N->getType() != MVT::isVoid &&
!II.ImplicitDefs.empty())
HandledReg = II.ImplicitDefs[0];
for (unsigned i = 0; i != Pattern.getDstRegs().size(); ++i) {
Record *Reg = Pattern.getDstRegs()[i];
if (!Reg->isSubClassOf("Register") || Reg == HandledReg) continue;
ResultVTs.push_back(getRegisterValueType(Reg, CGT));
}
}
// FIXME2: Instead of using the isVariadic flag on the instruction, we should