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Simplify some NEON assembly pseudo definitions.
Let the generic token alias definitions handle the data subtype suffices. We don't need explicit versions for each. llvm-svn: 148718
This commit is contained in:
Jim Grosbach
parent
ea859b30be
commit
0eeacbfe2e
@ -2029,75 +2029,6 @@ multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result> {
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// for instalias defs.
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class NEONDataTypeAsmPseudoInst<string opc, string dt, string asm, dag iops> :
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AsmPseudoInst<!strconcat(opc, dt, "\t", asm), iops>, Requires<[HasNEON]>;
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multiclass NEONDT8ReqAsmPseudoInst<string opc, string asm, dag iops> {
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def I8 : NEONDataTypeAsmPseudoInst<opc, ".i8", asm, iops>;
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def S8 : NEONDataTypeAsmPseudoInst<opc, ".s8", asm, iops>;
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def U8 : NEONDataTypeAsmPseudoInst<opc, ".u8", asm, iops>;
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def P8 : NEONDataTypeAsmPseudoInst<opc, ".p8", asm, iops>;
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}
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// NEONDT8ReqAsmPseudoInst plus plain ".8"
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multiclass NEONDT8AsmPseudoInst<string opc, string asm, dag iops> {
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def _8 : NEONDataTypeAsmPseudoInst<opc, ".8", asm, iops>;
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defm _ : NEONDT8ReqAsmPseudoInst<opc, asm, iops>;
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}
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multiclass NEONDT16ReqAsmPseudoInst<string opc, string asm, dag iops> {
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def I16 : NEONDataTypeAsmPseudoInst<opc, ".i16", asm, iops>;
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def S16 : NEONDataTypeAsmPseudoInst<opc, ".s16", asm, iops>;
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def U16 : NEONDataTypeAsmPseudoInst<opc, ".u16", asm, iops>;
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def P16 : NEONDataTypeAsmPseudoInst<opc, ".p16", asm, iops>;
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}
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// NEONDT16ReqAsmPseudoInst plus plain ".16"
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multiclass NEONDT16AsmPseudoInst<string opc, string asm, dag iops> {
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def _16 : NEONDataTypeAsmPseudoInst<opc, ".16", asm, iops>;
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defm _ : NEONDT16ReqAsmPseudoInst<opc, asm, iops>;
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}
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multiclass NEONDT32ReqAsmPseudoInst<string opc, string asm, dag iops> {
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def I32 : NEONDataTypeAsmPseudoInst<opc, ".i32", asm, iops>;
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def S32 : NEONDataTypeAsmPseudoInst<opc, ".s32", asm, iops>;
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def U32 : NEONDataTypeAsmPseudoInst<opc, ".u32", asm, iops>;
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def F32 : NEONDataTypeAsmPseudoInst<opc, ".f32", asm, iops>;
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def F : NEONDataTypeAsmPseudoInst<opc, ".f", asm, iops>;
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}
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// NEONDT32ReqAsmPseudoInst plus plain ".32"
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multiclass NEONDT32AsmPseudoInst<string opc, string asm, dag iops> {
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def _32 : NEONDataTypeAsmPseudoInst<opc, ".32", asm, iops>;
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defm _ : NEONDT32ReqAsmPseudoInst<opc, asm, iops>;
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}
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multiclass NEONDT64ReqAsmPseudoInst<string opc, string asm, dag iops> {
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def I64 : NEONDataTypeAsmPseudoInst<opc, ".i64", asm, iops>;
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def S64 : NEONDataTypeAsmPseudoInst<opc, ".s64", asm, iops>;
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def U64 : NEONDataTypeAsmPseudoInst<opc, ".u64", asm, iops>;
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def F64 : NEONDataTypeAsmPseudoInst<opc, ".f64", asm, iops>;
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def D : NEONDataTypeAsmPseudoInst<opc, ".d", asm, iops>;
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}
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// NEONDT64ReqAsmPseudoInst plus plain ".64"
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multiclass NEONDT64AsmPseudoInst<string opc, string asm, dag iops> {
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def _64 : NEONDataTypeAsmPseudoInst<opc, ".64", asm, iops>;
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defm _ : NEONDT64ReqAsmPseudoInst<opc, asm, iops>;
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}
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multiclass NEONDT64NoF64ReqAsmPseudoInst<string opc, string asm, dag iops> {
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def I64 : NEONDataTypeAsmPseudoInst<opc, ".i64", asm, iops>;
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def S64 : NEONDataTypeAsmPseudoInst<opc, ".s64", asm, iops>;
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def U64 : NEONDataTypeAsmPseudoInst<opc, ".u64", asm, iops>;
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def D : NEONDataTypeAsmPseudoInst<opc, ".d", asm, iops>;
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}
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// NEONDT64ReqAsmPseudoInst plus plain ".64"
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multiclass NEONDT64NoF64AsmPseudoInst<string opc, string asm, dag iops> {
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def _64 : NEONDataTypeAsmPseudoInst<opc, ".64", asm, iops>;
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defm _ : NEONDT64ReqAsmPseudoInst<opc, asm, iops>;
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}
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multiclass NEONDTAnyAsmPseudoInst<string opc, string asm, dag iops> {
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defm _ : NEONDT8AsmPseudoInst<opc, asm, iops>;
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defm _ : NEONDT16AsmPseudoInst<opc, asm, iops>;
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defm _ : NEONDT32AsmPseudoInst<opc, asm, iops>;
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defm _ : NEONDT64AsmPseudoInst<opc, asm, iops>;
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}
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multiclass NEONDTAnyNoF64AsmPseudoInst<string opc, string asm, dag iops> {
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defm _ : NEONDT8AsmPseudoInst<opc, asm, iops>;
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defm _ : NEONDT16AsmPseudoInst<opc, asm, iops>;
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defm _ : NEONDT32AsmPseudoInst<opc, asm, iops>;
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defm _ : NEONDT64NoF64AsmPseudoInst<opc, asm, iops>;
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}
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// Data type suffix token aliases. Implements Table A7-3 in the ARM ARM.
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def : TokenAlias<".s8", ".i8">;
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@ -5753,150 +5753,167 @@ def : NEONInstAlias<"vshr${p}.u64 $Vdn, $imm",
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// VLD1 single-lane pseudo-instructions. These need special handling for
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// the lane index that an InstAlias can't handle, so we use these instead.
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defm VLD1LNdAsm : NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr",
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def VLD1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr",
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(ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD1LNdAsm : NEONDT16AsmPseudoInst<"vld1${p}", "$list, $addr",
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def VLD1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr",
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(ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD1LNdAsm : NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr",
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def VLD1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr",
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(ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD1LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr!",
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def VLD1LNdWB_fixed_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr!",
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(ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD1LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vld1${p}", "$list, $addr!",
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def VLD1LNdWB_fixed_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr!",
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(ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD1LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr!",
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def VLD1LNdWB_fixed_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr!",
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(ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD1LNdWB_register_Asm :
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NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
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def VLD1LNdWB_register_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr, $Rm",
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(ins VecListOneDByteIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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defm VLD1LNdWB_register_Asm :
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NEONDT16AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
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def VLD1LNdWB_register_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr, $Rm",
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(ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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defm VLD1LNdWB_register_Asm :
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NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
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def VLD1LNdWB_register_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr, $Rm",
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(ins VecListOneDWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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// VST1 single-lane pseudo-instructions. These need special handling for
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// the lane index that an InstAlias can't handle, so we use these instead.
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defm VST1LNdAsm : NEONDT8AsmPseudoInst<"vst1${p}", "$list, $addr",
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def VST1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr",
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(ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VST1LNdAsm : NEONDT16AsmPseudoInst<"vst1${p}", "$list, $addr",
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def VST1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr",
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(ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VST1LNdAsm : NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr",
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def VST1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr",
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(ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VST1LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vst1${p}", "$list, $addr!",
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def VST1LNdWB_fixed_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr!",
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(ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VST1LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vst1${p}", "$list, $addr!",
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def VST1LNdWB_fixed_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr!",
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(ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VST1LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr!",
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def VST1LNdWB_fixed_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr!",
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(ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VST1LNdWB_register_Asm :
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NEONDT8AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm",
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def VST1LNdWB_register_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr, $Rm",
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(ins VecListOneDByteIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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defm VST1LNdWB_register_Asm :
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NEONDT16AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm",
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def VST1LNdWB_register_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr, $Rm",
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(ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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defm VST1LNdWB_register_Asm :
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NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm",
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def VST1LNdWB_register_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr, $Rm",
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(ins VecListOneDWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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// VLD2 single-lane pseudo-instructions. These need special handling for
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// the lane index that an InstAlias can't handle, so we use these instead.
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defm VLD2LNdAsm : NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr",
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def VLD2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr",
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(ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD2LNdAsm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr",
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def VLD2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
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(ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD2LNdAsm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr",
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def VLD2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
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(ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD2LNqAsm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr",
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def VLD2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
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(ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD2LNqAsm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr",
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def VLD2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
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(ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD2LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr!",
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def VLD2LNdWB_fixed_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr!",
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(ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD2LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr!",
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def VLD2LNdWB_fixed_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
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(ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD2LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr!",
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def VLD2LNdWB_fixed_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
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(ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD2LNqWB_fixed_Asm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr!",
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def VLD2LNqWB_fixed_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
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(ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD2LNqWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr!",
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def VLD2LNqWB_fixed_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
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(ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD2LNdWB_register_Asm :
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NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
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def VLD2LNdWB_register_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr, $Rm",
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(ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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defm VLD2LNdWB_register_Asm :
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NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
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def VLD2LNdWB_register_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
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(ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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defm VLD2LNdWB_register_Asm :
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NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
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def VLD2LNdWB_register_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
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(ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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defm VLD2LNqWB_register_Asm :
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NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
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def VLD2LNqWB_register_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
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(ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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defm VLD2LNqWB_register_Asm :
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NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
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def VLD2LNqWB_register_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
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(ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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// VST2 single-lane pseudo-instructions. These need special handling for
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// the lane index that an InstAlias can't handle, so we use these instead.
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defm VST2LNdAsm : NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr",
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def VST2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr",
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(ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VST2LNdAsm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr",
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def VST2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
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(ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VST2LNdAsm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr",
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def VST2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
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(ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VST2LNqAsm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr",
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def VST2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
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(ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VST2LNqAsm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr",
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def VST2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
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(ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VST2LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr!",
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def VST2LNdWB_fixed_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr!",
|
||||
(ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
|
||||
defm VST2LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr!",
|
||||
def VST2LNdWB_fixed_Asm_16 :
|
||||
NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
|
||||
(ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
|
||||
defm VST2LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr!",
|
||||
def VST2LNdWB_fixed_Asm_32 :
|
||||
NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
|
||||
(ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
|
||||
defm VST2LNqWB_fixed_Asm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr!",
|
||||
def VST2LNqWB_fixed_Asm_16 :
|
||||
NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
|
||||
(ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
|
||||
defm VST2LNqWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr!",
|
||||
def VST2LNqWB_fixed_Asm_32 :
|
||||
NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
|
||||
(ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
|
||||
defm VST2LNdWB_register_Asm :
|
||||
NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
|
||||
def VST2LNdWB_register_Asm_8 :
|
||||
NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr, $Rm",
|
||||
(ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
|
||||
rGPR:$Rm, pred:$p)>;
|
||||
defm VST2LNdWB_register_Asm :
|
||||
NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
|
||||
def VST2LNdWB_register_Asm_16 :
|
||||
NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
|
||||
(ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
|
||||
rGPR:$Rm, pred:$p)>;
|
||||
defm VST2LNdWB_register_Asm :
|
||||
NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
|
||||
def VST2LNdWB_register_Asm_32 :
|
||||
NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
|
||||
(ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
|
||||
rGPR:$Rm, pred:$p)>;
|
||||
defm VST2LNqWB_register_Asm :
|
||||
NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
|
||||
def VST2LNqWB_register_Asm_16 :
|
||||
NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
|
||||
(ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
|
||||
rGPR:$Rm, pred:$p)>;
|
||||
defm VST2LNqWB_register_Asm :
|
||||
NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
|
||||
def VST2LNqWB_register_Asm_32 :
|
||||
NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
|
||||
(ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
|
||||
rGPR:$Rm, pred:$p)>;
|
||||
|
||||
|
||||
// VMOV takes an optional datatype suffix
|
||||
defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
|
||||
(VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
|
||||
|
||||
@ -5147,128 +5147,80 @@ static unsigned getRealVSTLNOpcode(unsigned Opc, unsigned &Spacing) {
|
||||
switch(Opc) {
|
||||
default: assert(0 && "unexpected opcode!");
|
||||
// VST1LN
|
||||
case ARM::VST1LNdWB_fixed_Asm_8: case ARM::VST1LNdWB_fixed_Asm_P8:
|
||||
case ARM::VST1LNdWB_fixed_Asm_I8: case ARM::VST1LNdWB_fixed_Asm_S8:
|
||||
case ARM::VST1LNdWB_fixed_Asm_U8:
|
||||
case ARM::VST1LNdWB_fixed_Asm_8:
|
||||
Spacing = 1;
|
||||
return ARM::VST1LNd8_UPD;
|
||||
case ARM::VST1LNdWB_fixed_Asm_16: case ARM::VST1LNdWB_fixed_Asm_P16:
|
||||
case ARM::VST1LNdWB_fixed_Asm_I16: case ARM::VST1LNdWB_fixed_Asm_S16:
|
||||
case ARM::VST1LNdWB_fixed_Asm_U16:
|
||||
case ARM::VST1LNdWB_fixed_Asm_16:
|
||||
Spacing = 1;
|
||||
return ARM::VST1LNd16_UPD;
|
||||
case ARM::VST1LNdWB_fixed_Asm_32: case ARM::VST1LNdWB_fixed_Asm_F:
|
||||
case ARM::VST1LNdWB_fixed_Asm_F32: case ARM::VST1LNdWB_fixed_Asm_I32:
|
||||
case ARM::VST1LNdWB_fixed_Asm_S32: case ARM::VST1LNdWB_fixed_Asm_U32:
|
||||
case ARM::VST1LNdWB_fixed_Asm_32:
|
||||
Spacing = 1;
|
||||
return ARM::VST1LNd32_UPD;
|
||||
case ARM::VST1LNdWB_register_Asm_8: case ARM::VST1LNdWB_register_Asm_P8:
|
||||
case ARM::VST1LNdWB_register_Asm_I8: case ARM::VST1LNdWB_register_Asm_S8:
|
||||
case ARM::VST1LNdWB_register_Asm_U8:
|
||||
case ARM::VST1LNdWB_register_Asm_8:
|
||||
Spacing = 1;
|
||||
return ARM::VST1LNd8_UPD;
|
||||
case ARM::VST1LNdWB_register_Asm_16: case ARM::VST1LNdWB_register_Asm_P16:
|
||||
case ARM::VST1LNdWB_register_Asm_I16: case ARM::VST1LNdWB_register_Asm_S16:
|
||||
case ARM::VST1LNdWB_register_Asm_U16:
|
||||
case ARM::VST1LNdWB_register_Asm_16:
|
||||
Spacing = 1;
|
||||
return ARM::VST1LNd16_UPD;
|
||||
case ARM::VST1LNdWB_register_Asm_32: case ARM::VST1LNdWB_register_Asm_F:
|
||||
case ARM::VST1LNdWB_register_Asm_F32: case ARM::VST1LNdWB_register_Asm_I32:
|
||||
case ARM::VST1LNdWB_register_Asm_S32: case ARM::VST1LNdWB_register_Asm_U32:
|
||||
case ARM::VST1LNdWB_register_Asm_32:
|
||||
Spacing = 1;
|
||||
return ARM::VST1LNd32_UPD;
|
||||
case ARM::VST1LNdAsm_8: case ARM::VST1LNdAsm_P8:
|
||||
case ARM::VST1LNdAsm_I8: case ARM::VST1LNdAsm_S8:
|
||||
case ARM::VST1LNdAsm_U8:
|
||||
case ARM::VST1LNdAsm_8:
|
||||
Spacing = 1;
|
||||
return ARM::VST1LNd8;
|
||||
case ARM::VST1LNdAsm_16: case ARM::VST1LNdAsm_P16:
|
||||
case ARM::VST1LNdAsm_I16: case ARM::VST1LNdAsm_S16:
|
||||
case ARM::VST1LNdAsm_U16:
|
||||
case ARM::VST1LNdAsm_16:
|
||||
Spacing = 1;
|
||||
return ARM::VST1LNd16;
|
||||
case ARM::VST1LNdAsm_32: case ARM::VST1LNdAsm_F:
|
||||
case ARM::VST1LNdAsm_F32: case ARM::VST1LNdAsm_I32:
|
||||
case ARM::VST1LNdAsm_S32: case ARM::VST1LNdAsm_U32:
|
||||
case ARM::VST1LNdAsm_32:
|
||||
Spacing = 1;
|
||||
return ARM::VST1LNd32;
|
||||
|
||||
// VST2LN
|
||||
case ARM::VST2LNdWB_fixed_Asm_8: case ARM::VST2LNdWB_fixed_Asm_P8:
|
||||
case ARM::VST2LNdWB_fixed_Asm_I8: case ARM::VST2LNdWB_fixed_Asm_S8:
|
||||
case ARM::VST2LNdWB_fixed_Asm_U8:
|
||||
case ARM::VST2LNdWB_fixed_Asm_8:
|
||||
Spacing = 1;
|
||||
return ARM::VST2LNd8_UPD;
|
||||
case ARM::VST2LNdWB_fixed_Asm_16: case ARM::VST2LNdWB_fixed_Asm_P16:
|
||||
case ARM::VST2LNdWB_fixed_Asm_I16: case ARM::VST2LNdWB_fixed_Asm_S16:
|
||||
case ARM::VST2LNdWB_fixed_Asm_U16:
|
||||
case ARM::VST2LNdWB_fixed_Asm_16:
|
||||
Spacing = 1;
|
||||
return ARM::VST2LNd16_UPD;
|
||||
case ARM::VST2LNdWB_fixed_Asm_32: case ARM::VST2LNdWB_fixed_Asm_F:
|
||||
case ARM::VST2LNdWB_fixed_Asm_F32: case ARM::VST2LNdWB_fixed_Asm_I32:
|
||||
case ARM::VST2LNdWB_fixed_Asm_S32: case ARM::VST2LNdWB_fixed_Asm_U32:
|
||||
case ARM::VST2LNdWB_fixed_Asm_32:
|
||||
Spacing = 1;
|
||||
return ARM::VST2LNd32_UPD;
|
||||
case ARM::VST2LNqWB_fixed_Asm_16: case ARM::VST2LNqWB_fixed_Asm_P16:
|
||||
case ARM::VST2LNqWB_fixed_Asm_I16: case ARM::VST2LNqWB_fixed_Asm_S16:
|
||||
case ARM::VST2LNqWB_fixed_Asm_U16:
|
||||
case ARM::VST2LNqWB_fixed_Asm_16:
|
||||
Spacing = 2;
|
||||
return ARM::VST2LNq16_UPD;
|
||||
case ARM::VST2LNqWB_fixed_Asm_32: case ARM::VST2LNqWB_fixed_Asm_F:
|
||||
case ARM::VST2LNqWB_fixed_Asm_F32: case ARM::VST2LNqWB_fixed_Asm_I32:
|
||||
case ARM::VST2LNqWB_fixed_Asm_S32: case ARM::VST2LNqWB_fixed_Asm_U32:
|
||||
case ARM::VST2LNqWB_fixed_Asm_32:
|
||||
Spacing = 2;
|
||||
return ARM::VST2LNq32_UPD;
|
||||
|
||||
case ARM::VST2LNdWB_register_Asm_8: case ARM::VST2LNdWB_register_Asm_P8:
|
||||
case ARM::VST2LNdWB_register_Asm_I8: case ARM::VST2LNdWB_register_Asm_S8:
|
||||
case ARM::VST2LNdWB_register_Asm_U8:
|
||||
case ARM::VST2LNdWB_register_Asm_8:
|
||||
Spacing = 1;
|
||||
return ARM::VST2LNd8_UPD;
|
||||
case ARM::VST2LNdWB_register_Asm_16: case ARM::VST2LNdWB_register_Asm_P16:
|
||||
case ARM::VST2LNdWB_register_Asm_I16: case ARM::VST2LNdWB_register_Asm_S16:
|
||||
case ARM::VST2LNdWB_register_Asm_U16:
|
||||
case ARM::VST2LNdWB_register_Asm_16:
|
||||
Spacing = 1;
|
||||
return ARM::VST2LNd16_UPD;
|
||||
case ARM::VST2LNdWB_register_Asm_32: case ARM::VST2LNdWB_register_Asm_F:
|
||||
case ARM::VST2LNdWB_register_Asm_F32: case ARM::VST2LNdWB_register_Asm_I32:
|
||||
case ARM::VST2LNdWB_register_Asm_S32: case ARM::VST2LNdWB_register_Asm_U32:
|
||||
case ARM::VST2LNdWB_register_Asm_32:
|
||||
Spacing = 1;
|
||||
return ARM::VST2LNd32_UPD;
|
||||
case ARM::VST2LNqWB_register_Asm_16: case ARM::VST2LNqWB_register_Asm_P16:
|
||||
case ARM::VST2LNqWB_register_Asm_I16: case ARM::VST2LNqWB_register_Asm_S16:
|
||||
case ARM::VST2LNqWB_register_Asm_U16:
|
||||
case ARM::VST2LNqWB_register_Asm_16:
|
||||
Spacing = 2;
|
||||
return ARM::VST2LNq16_UPD;
|
||||
case ARM::VST2LNqWB_register_Asm_32: case ARM::VST2LNqWB_register_Asm_F:
|
||||
case ARM::VST2LNqWB_register_Asm_F32: case ARM::VST2LNqWB_register_Asm_I32:
|
||||
case ARM::VST2LNqWB_register_Asm_S32: case ARM::VST2LNqWB_register_Asm_U32:
|
||||
case ARM::VST2LNqWB_register_Asm_32:
|
||||
Spacing = 2;
|
||||
return ARM::VST2LNq32_UPD;
|
||||
|
||||
case ARM::VST2LNdAsm_8: case ARM::VST2LNdAsm_P8:
|
||||
case ARM::VST2LNdAsm_I8: case ARM::VST2LNdAsm_S8:
|
||||
case ARM::VST2LNdAsm_U8:
|
||||
case ARM::VST2LNdAsm_8:
|
||||
Spacing = 1;
|
||||
return ARM::VST2LNd8;
|
||||
case ARM::VST2LNdAsm_16: case ARM::VST2LNdAsm_P16:
|
||||
case ARM::VST2LNdAsm_I16: case ARM::VST2LNdAsm_S16:
|
||||
case ARM::VST2LNdAsm_U16:
|
||||
case ARM::VST2LNdAsm_16:
|
||||
Spacing = 1;
|
||||
return ARM::VST2LNd16;
|
||||
case ARM::VST2LNdAsm_32: case ARM::VST2LNdAsm_F:
|
||||
case ARM::VST2LNdAsm_F32: case ARM::VST2LNdAsm_I32:
|
||||
case ARM::VST2LNdAsm_S32: case ARM::VST2LNdAsm_U32:
|
||||
case ARM::VST2LNdAsm_32:
|
||||
Spacing = 1;
|
||||
return ARM::VST2LNd32;
|
||||
case ARM::VST2LNqAsm_16: case ARM::VST2LNqAsm_P16:
|
||||
case ARM::VST2LNqAsm_I16: case ARM::VST2LNqAsm_S16:
|
||||
case ARM::VST2LNqAsm_U16:
|
||||
case ARM::VST2LNqAsm_16:
|
||||
Spacing = 2;
|
||||
return ARM::VST2LNq16;
|
||||
case ARM::VST2LNqAsm_32: case ARM::VST2LNqAsm_F:
|
||||
case ARM::VST2LNqAsm_F32: case ARM::VST2LNqAsm_I32:
|
||||
case ARM::VST2LNqAsm_S32: case ARM::VST2LNqAsm_U32:
|
||||
case ARM::VST2LNqAsm_32:
|
||||
Spacing = 2;
|
||||
return ARM::VST2LNq32;
|
||||
}
|
||||
@ -5278,126 +5230,78 @@ static unsigned getRealVLDLNOpcode(unsigned Opc, unsigned &Spacing) {
|
||||
switch(Opc) {
|
||||
default: assert(0 && "unexpected opcode!");
|
||||
// VLD1LN
|
||||
case ARM::VLD1LNdWB_fixed_Asm_8: case ARM::VLD1LNdWB_fixed_Asm_P8:
|
||||
case ARM::VLD1LNdWB_fixed_Asm_I8: case ARM::VLD1LNdWB_fixed_Asm_S8:
|
||||
case ARM::VLD1LNdWB_fixed_Asm_U8:
|
||||
case ARM::VLD1LNdWB_fixed_Asm_8:
|
||||
Spacing = 1;
|
||||
return ARM::VLD1LNd8_UPD;
|
||||
case ARM::VLD1LNdWB_fixed_Asm_16: case ARM::VLD1LNdWB_fixed_Asm_P16:
|
||||
case ARM::VLD1LNdWB_fixed_Asm_I16: case ARM::VLD1LNdWB_fixed_Asm_S16:
|
||||
case ARM::VLD1LNdWB_fixed_Asm_U16:
|
||||
case ARM::VLD1LNdWB_fixed_Asm_16:
|
||||
Spacing = 1;
|
||||
return ARM::VLD1LNd16_UPD;
|
||||
case ARM::VLD1LNdWB_fixed_Asm_32: case ARM::VLD1LNdWB_fixed_Asm_F:
|
||||
case ARM::VLD1LNdWB_fixed_Asm_F32: case ARM::VLD1LNdWB_fixed_Asm_I32:
|
||||
case ARM::VLD1LNdWB_fixed_Asm_S32: case ARM::VLD1LNdWB_fixed_Asm_U32:
|
||||
case ARM::VLD1LNdWB_fixed_Asm_32:
|
||||
Spacing = 1;
|
||||
return ARM::VLD1LNd32_UPD;
|
||||
case ARM::VLD1LNdWB_register_Asm_8: case ARM::VLD1LNdWB_register_Asm_P8:
|
||||
case ARM::VLD1LNdWB_register_Asm_I8: case ARM::VLD1LNdWB_register_Asm_S8:
|
||||
case ARM::VLD1LNdWB_register_Asm_U8:
|
||||
case ARM::VLD1LNdWB_register_Asm_8:
|
||||
Spacing = 1;
|
||||
return ARM::VLD1LNd8_UPD;
|
||||
case ARM::VLD1LNdWB_register_Asm_16: case ARM::VLD1LNdWB_register_Asm_P16:
|
||||
case ARM::VLD1LNdWB_register_Asm_I16: case ARM::VLD1LNdWB_register_Asm_S16:
|
||||
case ARM::VLD1LNdWB_register_Asm_U16:
|
||||
case ARM::VLD1LNdWB_register_Asm_16:
|
||||
Spacing = 1;
|
||||
return ARM::VLD1LNd16_UPD;
|
||||
case ARM::VLD1LNdWB_register_Asm_32: case ARM::VLD1LNdWB_register_Asm_F:
|
||||
case ARM::VLD1LNdWB_register_Asm_F32: case ARM::VLD1LNdWB_register_Asm_I32:
|
||||
case ARM::VLD1LNdWB_register_Asm_S32: case ARM::VLD1LNdWB_register_Asm_U32:
|
||||
case ARM::VLD1LNdWB_register_Asm_32:
|
||||
Spacing = 1;
|
||||
return ARM::VLD1LNd32_UPD;
|
||||
case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_P8:
|
||||
case ARM::VLD1LNdAsm_I8: case ARM::VLD1LNdAsm_S8:
|
||||
case ARM::VLD1LNdAsm_U8:
|
||||
case ARM::VLD1LNdAsm_8:
|
||||
Spacing = 1;
|
||||
return ARM::VLD1LNd8;
|
||||
case ARM::VLD1LNdAsm_16: case ARM::VLD1LNdAsm_P16:
|
||||
case ARM::VLD1LNdAsm_I16: case ARM::VLD1LNdAsm_S16:
|
||||
case ARM::VLD1LNdAsm_U16:
|
||||
case ARM::VLD1LNdAsm_16:
|
||||
Spacing = 1;
|
||||
return ARM::VLD1LNd16;
|
||||
case ARM::VLD1LNdAsm_32: case ARM::VLD1LNdAsm_F:
|
||||
case ARM::VLD1LNdAsm_F32: case ARM::VLD1LNdAsm_I32:
|
||||
case ARM::VLD1LNdAsm_S32: case ARM::VLD1LNdAsm_U32:
|
||||
case ARM::VLD1LNdAsm_32:
|
||||
Spacing = 1;
|
||||
return ARM::VLD1LNd32;
|
||||
|
||||
// VLD2LN
|
||||
case ARM::VLD2LNdWB_fixed_Asm_8: case ARM::VLD2LNdWB_fixed_Asm_P8:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_I8: case ARM::VLD2LNdWB_fixed_Asm_S8:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_U8:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_8:
|
||||
Spacing = 1;
|
||||
return ARM::VLD2LNd8_UPD;
|
||||
case ARM::VLD2LNdWB_fixed_Asm_16: case ARM::VLD2LNdWB_fixed_Asm_P16:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_I16: case ARM::VLD2LNdWB_fixed_Asm_S16:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_U16:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_16:
|
||||
Spacing = 1;
|
||||
return ARM::VLD2LNd16_UPD;
|
||||
case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_F32: case ARM::VLD2LNdWB_fixed_Asm_I32:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_32:
|
||||
Spacing = 1;
|
||||
return ARM::VLD2LNd32_UPD;
|
||||
case ARM::VLD2LNqWB_fixed_Asm_16: case ARM::VLD2LNqWB_fixed_Asm_P16:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_I16: case ARM::VLD2LNqWB_fixed_Asm_S16:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_U16:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_16:
|
||||
Spacing = 1;
|
||||
return ARM::VLD2LNq16_UPD;
|
||||
case ARM::VLD2LNqWB_fixed_Asm_32: case ARM::VLD2LNqWB_fixed_Asm_F:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_F32: case ARM::VLD2LNqWB_fixed_Asm_I32:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_S32: case ARM::VLD2LNqWB_fixed_Asm_U32:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_32:
|
||||
Spacing = 2;
|
||||
return ARM::VLD2LNq32_UPD;
|
||||
case ARM::VLD2LNdWB_register_Asm_8: case ARM::VLD2LNdWB_register_Asm_P8:
|
||||
case ARM::VLD2LNdWB_register_Asm_I8: case ARM::VLD2LNdWB_register_Asm_S8:
|
||||
case ARM::VLD2LNdWB_register_Asm_U8:
|
||||
case ARM::VLD2LNdWB_register_Asm_8:
|
||||
Spacing = 1;
|
||||
return ARM::VLD2LNd8_UPD;
|
||||
case ARM::VLD2LNdWB_register_Asm_16: case ARM::VLD2LNdWB_register_Asm_P16:
|
||||
case ARM::VLD2LNdWB_register_Asm_I16: case ARM::VLD2LNdWB_register_Asm_S16:
|
||||
case ARM::VLD2LNdWB_register_Asm_U16:
|
||||
case ARM::VLD2LNdWB_register_Asm_16:
|
||||
Spacing = 1;
|
||||
return ARM::VLD2LNd16_UPD;
|
||||
case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F:
|
||||
case ARM::VLD2LNdWB_register_Asm_F32: case ARM::VLD2LNdWB_register_Asm_I32:
|
||||
case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32:
|
||||
case ARM::VLD2LNdWB_register_Asm_32:
|
||||
Spacing = 1;
|
||||
return ARM::VLD2LNd32_UPD;
|
||||
case ARM::VLD2LNqWB_register_Asm_16: case ARM::VLD2LNqWB_register_Asm_P16:
|
||||
case ARM::VLD2LNqWB_register_Asm_I16: case ARM::VLD2LNqWB_register_Asm_S16:
|
||||
case ARM::VLD2LNqWB_register_Asm_U16:
|
||||
case ARM::VLD2LNqWB_register_Asm_16:
|
||||
Spacing = 2;
|
||||
return ARM::VLD2LNq16_UPD;
|
||||
case ARM::VLD2LNqWB_register_Asm_32: case ARM::VLD2LNqWB_register_Asm_F:
|
||||
case ARM::VLD2LNqWB_register_Asm_F32: case ARM::VLD2LNqWB_register_Asm_I32:
|
||||
case ARM::VLD2LNqWB_register_Asm_S32: case ARM::VLD2LNqWB_register_Asm_U32:
|
||||
case ARM::VLD2LNqWB_register_Asm_32:
|
||||
Spacing = 2;
|
||||
return ARM::VLD2LNq32_UPD;
|
||||
case ARM::VLD2LNdAsm_8: case ARM::VLD2LNdAsm_P8:
|
||||
case ARM::VLD2LNdAsm_I8: case ARM::VLD2LNdAsm_S8:
|
||||
case ARM::VLD2LNdAsm_U8:
|
||||
case ARM::VLD2LNdAsm_8:
|
||||
Spacing = 1;
|
||||
return ARM::VLD2LNd8;
|
||||
case ARM::VLD2LNdAsm_16: case ARM::VLD2LNdAsm_P16:
|
||||
case ARM::VLD2LNdAsm_I16: case ARM::VLD2LNdAsm_S16:
|
||||
case ARM::VLD2LNdAsm_U16:
|
||||
case ARM::VLD2LNdAsm_16:
|
||||
Spacing = 1;
|
||||
return ARM::VLD2LNd16;
|
||||
case ARM::VLD2LNdAsm_32: case ARM::VLD2LNdAsm_F:
|
||||
case ARM::VLD2LNdAsm_F32: case ARM::VLD2LNdAsm_I32:
|
||||
case ARM::VLD2LNdAsm_S32: case ARM::VLD2LNdAsm_U32:
|
||||
case ARM::VLD2LNdAsm_32:
|
||||
Spacing = 1;
|
||||
return ARM::VLD2LNd32;
|
||||
case ARM::VLD2LNqAsm_16: case ARM::VLD2LNqAsm_P16:
|
||||
case ARM::VLD2LNqAsm_I16: case ARM::VLD2LNqAsm_S16:
|
||||
case ARM::VLD2LNqAsm_U16:
|
||||
case ARM::VLD2LNqAsm_16:
|
||||
Spacing = 2;
|
||||
return ARM::VLD2LNq16;
|
||||
case ARM::VLD2LNqAsm_32: case ARM::VLD2LNqAsm_F:
|
||||
case ARM::VLD2LNqAsm_F32: case ARM::VLD2LNqAsm_I32:
|
||||
case ARM::VLD2LNqAsm_S32: case ARM::VLD2LNqAsm_U32:
|
||||
case ARM::VLD2LNqAsm_32:
|
||||
Spacing = 2;
|
||||
return ARM::VLD2LNq32;
|
||||
}
|
||||
@ -5424,14 +5328,9 @@ processInstruction(MCInst &Inst,
|
||||
Inst.setOpcode(ARM::t2LDRSHpci);
|
||||
return true;
|
||||
// Handle NEON VST complex aliases.
|
||||
case ARM::VST1LNdWB_register_Asm_8: case ARM::VST1LNdWB_register_Asm_P8:
|
||||
case ARM::VST1LNdWB_register_Asm_I8: case ARM::VST1LNdWB_register_Asm_S8:
|
||||
case ARM::VST1LNdWB_register_Asm_U8: case ARM::VST1LNdWB_register_Asm_16:
|
||||
case ARM::VST1LNdWB_register_Asm_P16: case ARM::VST1LNdWB_register_Asm_I16:
|
||||
case ARM::VST1LNdWB_register_Asm_S16: case ARM::VST1LNdWB_register_Asm_U16:
|
||||
case ARM::VST1LNdWB_register_Asm_32: case ARM::VST1LNdWB_register_Asm_F:
|
||||
case ARM::VST1LNdWB_register_Asm_F32: case ARM::VST1LNdWB_register_Asm_I32:
|
||||
case ARM::VST1LNdWB_register_Asm_S32: case ARM::VST1LNdWB_register_Asm_U32: {
|
||||
case ARM::VST1LNdWB_register_Asm_8:
|
||||
case ARM::VST1LNdWB_register_Asm_16:
|
||||
case ARM::VST1LNdWB_register_Asm_32: {
|
||||
MCInst TmpInst;
|
||||
// Shuffle the operands around so the lane index operand is in the
|
||||
// right place.
|
||||
@ -5449,20 +5348,11 @@ processInstruction(MCInst &Inst,
|
||||
return true;
|
||||
}
|
||||
|
||||
case ARM::VST2LNdWB_register_Asm_8: case ARM::VST2LNdWB_register_Asm_P8:
|
||||
case ARM::VST2LNdWB_register_Asm_I8: case ARM::VST2LNdWB_register_Asm_S8:
|
||||
case ARM::VST2LNdWB_register_Asm_U8: case ARM::VST2LNdWB_register_Asm_16:
|
||||
case ARM::VST2LNdWB_register_Asm_P16: case ARM::VST2LNdWB_register_Asm_I16:
|
||||
case ARM::VST2LNdWB_register_Asm_S16: case ARM::VST2LNdWB_register_Asm_U16:
|
||||
case ARM::VST2LNdWB_register_Asm_32: case ARM::VST2LNdWB_register_Asm_F:
|
||||
case ARM::VST2LNdWB_register_Asm_F32: case ARM::VST2LNdWB_register_Asm_I32:
|
||||
case ARM::VST2LNdWB_register_Asm_S32: case ARM::VST2LNdWB_register_Asm_U32:
|
||||
case ARM::VST2LNqWB_register_Asm_16: case ARM::VST2LNqWB_register_Asm_P16:
|
||||
case ARM::VST2LNqWB_register_Asm_I16: case ARM::VST2LNqWB_register_Asm_S16:
|
||||
case ARM::VST2LNqWB_register_Asm_U16: case ARM::VST2LNqWB_register_Asm_32:
|
||||
case ARM::VST2LNqWB_register_Asm_F: case ARM::VST2LNqWB_register_Asm_F32:
|
||||
case ARM::VST2LNqWB_register_Asm_I32: case ARM::VST2LNqWB_register_Asm_S32:
|
||||
case ARM::VST2LNqWB_register_Asm_U32: {
|
||||
case ARM::VST2LNdWB_register_Asm_8:
|
||||
case ARM::VST2LNdWB_register_Asm_16:
|
||||
case ARM::VST2LNdWB_register_Asm_32:
|
||||
case ARM::VST2LNqWB_register_Asm_16:
|
||||
case ARM::VST2LNqWB_register_Asm_32: {
|
||||
MCInst TmpInst;
|
||||
// Shuffle the operands around so the lane index operand is in the
|
||||
// right place.
|
||||
@ -5481,14 +5371,9 @@ processInstruction(MCInst &Inst,
|
||||
Inst = TmpInst;
|
||||
return true;
|
||||
}
|
||||
case ARM::VST1LNdWB_fixed_Asm_8: case ARM::VST1LNdWB_fixed_Asm_P8:
|
||||
case ARM::VST1LNdWB_fixed_Asm_I8: case ARM::VST1LNdWB_fixed_Asm_S8:
|
||||
case ARM::VST1LNdWB_fixed_Asm_U8: case ARM::VST1LNdWB_fixed_Asm_16:
|
||||
case ARM::VST1LNdWB_fixed_Asm_P16: case ARM::VST1LNdWB_fixed_Asm_I16:
|
||||
case ARM::VST1LNdWB_fixed_Asm_S16: case ARM::VST1LNdWB_fixed_Asm_U16:
|
||||
case ARM::VST1LNdWB_fixed_Asm_32: case ARM::VST1LNdWB_fixed_Asm_F:
|
||||
case ARM::VST1LNdWB_fixed_Asm_F32: case ARM::VST1LNdWB_fixed_Asm_I32:
|
||||
case ARM::VST1LNdWB_fixed_Asm_S32: case ARM::VST1LNdWB_fixed_Asm_U32: {
|
||||
case ARM::VST1LNdWB_fixed_Asm_8:
|
||||
case ARM::VST1LNdWB_fixed_Asm_16:
|
||||
case ARM::VST1LNdWB_fixed_Asm_32: {
|
||||
MCInst TmpInst;
|
||||
// Shuffle the operands around so the lane index operand is in the
|
||||
// right place.
|
||||
@ -5506,20 +5391,11 @@ processInstruction(MCInst &Inst,
|
||||
return true;
|
||||
}
|
||||
|
||||
case ARM::VST2LNdWB_fixed_Asm_8: case ARM::VST2LNdWB_fixed_Asm_P8:
|
||||
case ARM::VST2LNdWB_fixed_Asm_I8: case ARM::VST2LNdWB_fixed_Asm_S8:
|
||||
case ARM::VST2LNdWB_fixed_Asm_U8: case ARM::VST2LNdWB_fixed_Asm_16:
|
||||
case ARM::VST2LNdWB_fixed_Asm_P16: case ARM::VST2LNdWB_fixed_Asm_I16:
|
||||
case ARM::VST2LNdWB_fixed_Asm_S16: case ARM::VST2LNdWB_fixed_Asm_U16:
|
||||
case ARM::VST2LNdWB_fixed_Asm_32: case ARM::VST2LNdWB_fixed_Asm_F:
|
||||
case ARM::VST2LNdWB_fixed_Asm_F32: case ARM::VST2LNdWB_fixed_Asm_I32:
|
||||
case ARM::VST2LNdWB_fixed_Asm_S32: case ARM::VST2LNdWB_fixed_Asm_U32:
|
||||
case ARM::VST2LNqWB_fixed_Asm_16: case ARM::VST2LNqWB_fixed_Asm_P16:
|
||||
case ARM::VST2LNqWB_fixed_Asm_I16: case ARM::VST2LNqWB_fixed_Asm_S16:
|
||||
case ARM::VST2LNqWB_fixed_Asm_U16: case ARM::VST2LNqWB_fixed_Asm_32:
|
||||
case ARM::VST2LNqWB_fixed_Asm_F: case ARM::VST2LNqWB_fixed_Asm_F32:
|
||||
case ARM::VST2LNqWB_fixed_Asm_I32: case ARM::VST2LNqWB_fixed_Asm_S32:
|
||||
case ARM::VST2LNqWB_fixed_Asm_U32: {
|
||||
case ARM::VST2LNdWB_fixed_Asm_8:
|
||||
case ARM::VST2LNdWB_fixed_Asm_16:
|
||||
case ARM::VST2LNdWB_fixed_Asm_32:
|
||||
case ARM::VST2LNqWB_fixed_Asm_16:
|
||||
case ARM::VST2LNqWB_fixed_Asm_32: {
|
||||
MCInst TmpInst;
|
||||
// Shuffle the operands around so the lane index operand is in the
|
||||
// right place.
|
||||
@ -5538,12 +5414,9 @@ processInstruction(MCInst &Inst,
|
||||
Inst = TmpInst;
|
||||
return true;
|
||||
}
|
||||
case ARM::VST1LNdAsm_8: case ARM::VST1LNdAsm_P8: case ARM::VST1LNdAsm_I8:
|
||||
case ARM::VST1LNdAsm_S8: case ARM::VST1LNdAsm_U8: case ARM::VST1LNdAsm_16:
|
||||
case ARM::VST1LNdAsm_P16: case ARM::VST1LNdAsm_I16: case ARM::VST1LNdAsm_S16:
|
||||
case ARM::VST1LNdAsm_U16: case ARM::VST1LNdAsm_32: case ARM::VST1LNdAsm_F:
|
||||
case ARM::VST1LNdAsm_F32: case ARM::VST1LNdAsm_I32: case ARM::VST1LNdAsm_S32:
|
||||
case ARM::VST1LNdAsm_U32: {
|
||||
case ARM::VST1LNdAsm_8:
|
||||
case ARM::VST1LNdAsm_16:
|
||||
case ARM::VST1LNdAsm_32: {
|
||||
MCInst TmpInst;
|
||||
// Shuffle the operands around so the lane index operand is in the
|
||||
// right place.
|
||||
@ -5559,15 +5432,11 @@ processInstruction(MCInst &Inst,
|
||||
return true;
|
||||
}
|
||||
|
||||
case ARM::VST2LNdAsm_8: case ARM::VST2LNdAsm_P8: case ARM::VST2LNdAsm_I8:
|
||||
case ARM::VST2LNdAsm_S8: case ARM::VST2LNdAsm_U8: case ARM::VST2LNdAsm_16:
|
||||
case ARM::VST2LNdAsm_P16: case ARM::VST2LNdAsm_I16: case ARM::VST2LNdAsm_S16:
|
||||
case ARM::VST2LNdAsm_U16: case ARM::VST2LNdAsm_32: case ARM::VST2LNdAsm_F:
|
||||
case ARM::VST2LNdAsm_F32: case ARM::VST2LNdAsm_I32: case ARM::VST2LNdAsm_S32:
|
||||
case ARM::VST2LNdAsm_U32: case ARM::VST2LNqAsm_16: case ARM::VST2LNqAsm_P16:
|
||||
case ARM::VST2LNqAsm_I16: case ARM::VST2LNqAsm_S16: case ARM::VST2LNqAsm_U16:
|
||||
case ARM::VST2LNqAsm_32: case ARM::VST2LNqAsm_F: case ARM::VST2LNqAsm_F32:
|
||||
case ARM::VST2LNqAsm_I32: case ARM::VST2LNqAsm_S32: case ARM::VST2LNqAsm_U32:{
|
||||
case ARM::VST2LNdAsm_8:
|
||||
case ARM::VST2LNdAsm_16:
|
||||
case ARM::VST2LNdAsm_32:
|
||||
case ARM::VST2LNqAsm_16:
|
||||
case ARM::VST2LNqAsm_32: {
|
||||
MCInst TmpInst;
|
||||
// Shuffle the operands around so the lane index operand is in the
|
||||
// right place.
|
||||
@ -5585,14 +5454,9 @@ processInstruction(MCInst &Inst,
|
||||
return true;
|
||||
}
|
||||
// Handle NEON VLD complex aliases.
|
||||
case ARM::VLD1LNdWB_register_Asm_8: case ARM::VLD1LNdWB_register_Asm_P8:
|
||||
case ARM::VLD1LNdWB_register_Asm_I8: case ARM::VLD1LNdWB_register_Asm_S8:
|
||||
case ARM::VLD1LNdWB_register_Asm_U8: case ARM::VLD1LNdWB_register_Asm_16:
|
||||
case ARM::VLD1LNdWB_register_Asm_P16: case ARM::VLD1LNdWB_register_Asm_I16:
|
||||
case ARM::VLD1LNdWB_register_Asm_S16: case ARM::VLD1LNdWB_register_Asm_U16:
|
||||
case ARM::VLD1LNdWB_register_Asm_32: case ARM::VLD1LNdWB_register_Asm_F:
|
||||
case ARM::VLD1LNdWB_register_Asm_F32: case ARM::VLD1LNdWB_register_Asm_I32:
|
||||
case ARM::VLD1LNdWB_register_Asm_S32: case ARM::VLD1LNdWB_register_Asm_U32: {
|
||||
case ARM::VLD1LNdWB_register_Asm_8:
|
||||
case ARM::VLD1LNdWB_register_Asm_16:
|
||||
case ARM::VLD1LNdWB_register_Asm_32: {
|
||||
MCInst TmpInst;
|
||||
// Shuffle the operands around so the lane index operand is in the
|
||||
// right place.
|
||||
@ -5611,20 +5475,11 @@ processInstruction(MCInst &Inst,
|
||||
return true;
|
||||
}
|
||||
|
||||
case ARM::VLD2LNdWB_register_Asm_8: case ARM::VLD2LNdWB_register_Asm_P8:
|
||||
case ARM::VLD2LNdWB_register_Asm_I8: case ARM::VLD2LNdWB_register_Asm_S8:
|
||||
case ARM::VLD2LNdWB_register_Asm_U8: case ARM::VLD2LNdWB_register_Asm_16:
|
||||
case ARM::VLD2LNdWB_register_Asm_P16: case ARM::VLD2LNdWB_register_Asm_I16:
|
||||
case ARM::VLD2LNdWB_register_Asm_S16: case ARM::VLD2LNdWB_register_Asm_U16:
|
||||
case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F:
|
||||
case ARM::VLD2LNdWB_register_Asm_F32: case ARM::VLD2LNdWB_register_Asm_I32:
|
||||
case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32:
|
||||
case ARM::VLD2LNqWB_register_Asm_16: case ARM::VLD2LNqWB_register_Asm_P16:
|
||||
case ARM::VLD2LNqWB_register_Asm_I16: case ARM::VLD2LNqWB_register_Asm_S16:
|
||||
case ARM::VLD2LNqWB_register_Asm_U16: case ARM::VLD2LNqWB_register_Asm_32:
|
||||
case ARM::VLD2LNqWB_register_Asm_F: case ARM::VLD2LNqWB_register_Asm_F32:
|
||||
case ARM::VLD2LNqWB_register_Asm_I32: case ARM::VLD2LNqWB_register_Asm_S32:
|
||||
case ARM::VLD2LNqWB_register_Asm_U32: {
|
||||
case ARM::VLD2LNdWB_register_Asm_8:
|
||||
case ARM::VLD2LNdWB_register_Asm_16:
|
||||
case ARM::VLD2LNdWB_register_Asm_32:
|
||||
case ARM::VLD2LNqWB_register_Asm_16:
|
||||
case ARM::VLD2LNqWB_register_Asm_32: {
|
||||
MCInst TmpInst;
|
||||
// Shuffle the operands around so the lane index operand is in the
|
||||
// right place.
|
||||
@ -5647,14 +5502,9 @@ processInstruction(MCInst &Inst,
|
||||
return true;
|
||||
}
|
||||
|
||||
case ARM::VLD1LNdWB_fixed_Asm_8: case ARM::VLD1LNdWB_fixed_Asm_P8:
|
||||
case ARM::VLD1LNdWB_fixed_Asm_I8: case ARM::VLD1LNdWB_fixed_Asm_S8:
|
||||
case ARM::VLD1LNdWB_fixed_Asm_U8: case ARM::VLD1LNdWB_fixed_Asm_16:
|
||||
case ARM::VLD1LNdWB_fixed_Asm_P16: case ARM::VLD1LNdWB_fixed_Asm_I16:
|
||||
case ARM::VLD1LNdWB_fixed_Asm_S16: case ARM::VLD1LNdWB_fixed_Asm_U16:
|
||||
case ARM::VLD1LNdWB_fixed_Asm_32: case ARM::VLD1LNdWB_fixed_Asm_F:
|
||||
case ARM::VLD1LNdWB_fixed_Asm_F32: case ARM::VLD1LNdWB_fixed_Asm_I32:
|
||||
case ARM::VLD1LNdWB_fixed_Asm_S32: case ARM::VLD1LNdWB_fixed_Asm_U32: {
|
||||
case ARM::VLD1LNdWB_fixed_Asm_8:
|
||||
case ARM::VLD1LNdWB_fixed_Asm_16:
|
||||
case ARM::VLD1LNdWB_fixed_Asm_32: {
|
||||
MCInst TmpInst;
|
||||
// Shuffle the operands around so the lane index operand is in the
|
||||
// right place.
|
||||
@ -5673,20 +5523,11 @@ processInstruction(MCInst &Inst,
|
||||
return true;
|
||||
}
|
||||
|
||||
case ARM::VLD2LNdWB_fixed_Asm_8: case ARM::VLD2LNdWB_fixed_Asm_P8:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_I8: case ARM::VLD2LNdWB_fixed_Asm_S8:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_U8: case ARM::VLD2LNdWB_fixed_Asm_16:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_P16: case ARM::VLD2LNdWB_fixed_Asm_I16:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_S16: case ARM::VLD2LNdWB_fixed_Asm_U16:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_F32: case ARM::VLD2LNdWB_fixed_Asm_I32:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_16: case ARM::VLD2LNqWB_fixed_Asm_P16:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_I16: case ARM::VLD2LNqWB_fixed_Asm_S16:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_U16: case ARM::VLD2LNqWB_fixed_Asm_32:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_F: case ARM::VLD2LNqWB_fixed_Asm_F32:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_I32: case ARM::VLD2LNqWB_fixed_Asm_S32:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_U32: {
|
||||
case ARM::VLD2LNdWB_fixed_Asm_8:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_16:
|
||||
case ARM::VLD2LNdWB_fixed_Asm_32:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_16:
|
||||
case ARM::VLD2LNqWB_fixed_Asm_32: {
|
||||
MCInst TmpInst;
|
||||
// Shuffle the operands around so the lane index operand is in the
|
||||
// right place.
|
||||
@ -5709,12 +5550,9 @@ processInstruction(MCInst &Inst,
|
||||
return true;
|
||||
}
|
||||
|
||||
case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_P8: case ARM::VLD1LNdAsm_I8:
|
||||
case ARM::VLD1LNdAsm_S8: case ARM::VLD1LNdAsm_U8: case ARM::VLD1LNdAsm_16:
|
||||
case ARM::VLD1LNdAsm_P16: case ARM::VLD1LNdAsm_I16: case ARM::VLD1LNdAsm_S16:
|
||||
case ARM::VLD1LNdAsm_U16: case ARM::VLD1LNdAsm_32: case ARM::VLD1LNdAsm_F:
|
||||
case ARM::VLD1LNdAsm_F32: case ARM::VLD1LNdAsm_I32: case ARM::VLD1LNdAsm_S32:
|
||||
case ARM::VLD1LNdAsm_U32: {
|
||||
case ARM::VLD1LNdAsm_8:
|
||||
case ARM::VLD1LNdAsm_16:
|
||||
case ARM::VLD1LNdAsm_32: {
|
||||
MCInst TmpInst;
|
||||
// Shuffle the operands around so the lane index operand is in the
|
||||
// right place.
|
||||
@ -5731,16 +5569,11 @@ processInstruction(MCInst &Inst,
|
||||
return true;
|
||||
}
|
||||
|
||||
case ARM::VLD2LNdAsm_8: case ARM::VLD2LNdAsm_P8: case ARM::VLD2LNdAsm_I8:
|
||||
case ARM::VLD2LNdAsm_S8: case ARM::VLD2LNdAsm_U8: case ARM::VLD2LNdAsm_16:
|
||||
case ARM::VLD2LNdAsm_P16: case ARM::VLD2LNdAsm_I16: case ARM::VLD2LNdAsm_S16:
|
||||
case ARM::VLD2LNdAsm_U16: case ARM::VLD2LNdAsm_32: case ARM::VLD2LNdAsm_F:
|
||||
case ARM::VLD2LNdAsm_F32: case ARM::VLD2LNdAsm_I32: case ARM::VLD2LNdAsm_S32:
|
||||
case ARM::VLD2LNdAsm_U32: case ARM::VLD2LNqAsm_16: case ARM::VLD2LNqAsm_P16:
|
||||
case ARM::VLD2LNqAsm_I16: case ARM::VLD2LNqAsm_S16: case ARM::VLD2LNqAsm_U16:
|
||||
case ARM::VLD2LNqAsm_32: case ARM::VLD2LNqAsm_F: case ARM::VLD2LNqAsm_F32:
|
||||
case ARM::VLD2LNqAsm_I32: case ARM::VLD2LNqAsm_S32:
|
||||
case ARM::VLD2LNqAsm_U32: {
|
||||
case ARM::VLD2LNdAsm_8:
|
||||
case ARM::VLD2LNdAsm_16:
|
||||
case ARM::VLD2LNdAsm_32:
|
||||
case ARM::VLD2LNqAsm_16:
|
||||
case ARM::VLD2LNqAsm_32: {
|
||||
MCInst TmpInst;
|
||||
// Shuffle the operands around so the lane index operand is in the
|
||||
// right place.
|
||||
|
||||
@ -99,21 +99,21 @@
|
||||
|
||||
|
||||
vst2.8 {d16[1], d17[1]}, [r0, :16]
|
||||
vst2.16 {d16[1], d17[1]}, [r0, :32]
|
||||
vst2.32 {d16[1], d17[1]}, [r0]
|
||||
vst2.16 {d17[1], d19[1]}, [r0]
|
||||
vst2.32 {d17[0], d19[0]}, [r0, :64]
|
||||
vst2.p16 {d16[1], d17[1]}, [r0, :32]
|
||||
vst2.i32 {d16[1], d17[1]}, [r0]
|
||||
vst2.u16 {d17[1], d19[1]}, [r0]
|
||||
vst2.f32 {d17[0], d19[0]}, [r0, :64]
|
||||
|
||||
vst2.8 {d2[4], d3[4]}, [r2], r3
|
||||
vst2.8 {d2[4], d3[4]}, [r2]!
|
||||
vst2.8 {d2[4], d3[4]}, [r2]
|
||||
vst2.u8 {d2[4], d3[4]}, [r2]!
|
||||
vst2.p8 {d2[4], d3[4]}, [r2]
|
||||
|
||||
vst2.16 {d17[1], d19[1]}, [r0]
|
||||
vst2.32 {d17[0], d19[0]}, [r0, :64]
|
||||
vst2.16 {d7[1], d9[1]}, [r1]!
|
||||
vst2.i16 {d7[1], d9[1]}, [r1]!
|
||||
vst2.32 {d6[0], d8[0]}, [r2, :64]!
|
||||
vst2.16 {d2[1], d4[1]}, [r3], r5
|
||||
vst2.32 {d5[0], d7[0]}, [r4, :64], r7
|
||||
vst2.u32 {d5[0], d7[0]}, [r4, :64], r7
|
||||
|
||||
@ CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xc0,0xf4]
|
||||
@ CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xc0,0xf4]
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user