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[AMDGPU] SDWA: make pass global
Summary: Remove checks for basic blocks. Reviewers: vpykhtin, rampitec, arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D31935 llvm-svn: 300040
This commit is contained in:
Sam Kolton
parent
1719856e12
commit
0f0e788e26
@ -63,7 +63,7 @@ public:
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void matchSDWAOperands(MachineBasicBlock &MBB);
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void matchSDWAOperands(MachineFunction &MF);
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bool convertToSDWA(MachineInstr &MI, const SDWAOperandsVector &SDWAOperands);
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StringRef getPassName() const override { return "SI Peephole SDWA"; }
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@ -196,11 +196,6 @@ static raw_ostream& operator<<(raw_ostream &OS, const SDWADstOperand &Dst) {
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#endif
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static bool isSameBB(const MachineInstr *FirstMI, const MachineInstr *SecondMI) {
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assert(FirstMI && SecondMI);
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return FirstMI->getParent() == SecondMI->getParent();
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}
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static void copyRegOperand(MachineOperand &To, const MachineOperand &From) {
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assert(To.isReg() && From.isReg());
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To.setReg(From.getReg());
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@ -266,10 +261,9 @@ MachineInstr *SDWASrcOperand::potentialToConvert(const SIInstrInfo *TII) {
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if (!isSubregOf(*Replaced, PotentialMO, MRI->getTargetRegisterInfo()))
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continue;
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// If there exist use of dst in another basic block or use of superreg of
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// dst then we should not combine this opernad
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if (!isSameBB(PotentialMO.getParent(), getParentInst()) ||
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!isSameReg(PotentialMO, *Replaced))
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// If there exist use of superreg of dst then we should not combine this
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// opernad
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if (!isSameReg(PotentialMO, *Replaced))
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return nullptr;
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// Check that PotentialMI is only instruction that uses dst reg
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@ -329,8 +323,7 @@ MachineInstr *SDWADstOperand::potentialToConvert(const SIInstrInfo *TII) {
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if (!isSubregOf(*Replaced, PotentialMO, MRI->getTargetRegisterInfo()))
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continue;
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if (!isSameBB(getParentInst(), PotentialMO.getParent()) ||
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!isSameReg(*Replaced, PotentialMO))
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if (!isSameReg(*Replaced, PotentialMO))
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return nullptr;
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// Check that ParentMI is the only instruction that uses replaced register
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@ -389,7 +382,7 @@ Optional<int64_t> SIPeepholeSDWA::foldToImm(const MachineOperand &Op) const {
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continue;
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const MachineInstr *DefInst = Def.getParent();
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if (!TII->isFoldableCopy(*DefInst) || !isSameBB(Op.getParent(), DefInst))
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if (!TII->isFoldableCopy(*DefInst))
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return None;
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const MachineOperand &Copied = DefInst->getOperand(1);
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@ -403,179 +396,181 @@ Optional<int64_t> SIPeepholeSDWA::foldToImm(const MachineOperand &Op) const {
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return None;
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}
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void SIPeepholeSDWA::matchSDWAOperands(MachineBasicBlock &MBB) {
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for (MachineInstr &MI : MBB) {
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unsigned Opcode = MI.getOpcode();
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switch (Opcode) {
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case AMDGPU::V_LSHRREV_B32_e32:
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case AMDGPU::V_ASHRREV_I32_e32:
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case AMDGPU::V_LSHLREV_B32_e32: {
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// from: v_lshrrev_b32_e32 v1, 16/24, v0
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// to SDWA src:v0 src_sel:WORD_1/BYTE_3
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void SIPeepholeSDWA::matchSDWAOperands(MachineFunction &MF) {
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : MBB) {
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unsigned Opcode = MI.getOpcode();
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switch (Opcode) {
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case AMDGPU::V_LSHRREV_B32_e32:
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case AMDGPU::V_ASHRREV_I32_e32:
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case AMDGPU::V_LSHLREV_B32_e32: {
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// from: v_lshrrev_b32_e32 v1, 16/24, v0
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// to SDWA src:v0 src_sel:WORD_1/BYTE_3
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// from: v_ashrrev_i32_e32 v1, 16/24, v0
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// to SDWA src:v0 src_sel:WORD_1/BYTE_3 sext:1
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// from: v_ashrrev_i32_e32 v1, 16/24, v0
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// to SDWA src:v0 src_sel:WORD_1/BYTE_3 sext:1
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// from: v_lshlrev_b32_e32 v1, 16/24, v0
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// to SDWA dst:v1 dst_sel:WORD_1/BYTE_3 dst_unused:UNUSED_PAD
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MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
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auto Imm = foldToImm(*Src0);
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if (!Imm)
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// from: v_lshlrev_b32_e32 v1, 16/24, v0
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// to SDWA dst:v1 dst_sel:WORD_1/BYTE_3 dst_unused:UNUSED_PAD
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MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
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auto Imm = foldToImm(*Src0);
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if (!Imm)
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break;
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if (*Imm != 16 && *Imm != 24)
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break;
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MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
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MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
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if (TRI->isPhysicalRegister(Src1->getReg()) ||
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TRI->isPhysicalRegister(Dst->getReg()))
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break;
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if (Opcode == AMDGPU::V_LSHLREV_B32_e32) {
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auto SDWADst = make_unique<SDWADstOperand>(
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Dst, Src1, *Imm == 16 ? WORD_1 : BYTE_3, UNUSED_PAD);
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DEBUG(dbgs() << "Match: " << MI << "To: " << *SDWADst << '\n');
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SDWAOperands[&MI] = std::move(SDWADst);
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++NumSDWAPatternsFound;
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} else {
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auto SDWASrc = make_unique<SDWASrcOperand>(
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Src1, Dst, *Imm == 16 ? WORD_1 : BYTE_3, false, false,
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Opcode == AMDGPU::V_LSHRREV_B32_e32 ? false : true);
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DEBUG(dbgs() << "Match: " << MI << "To: " << *SDWASrc << '\n');
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SDWAOperands[&MI] = std::move(SDWASrc);
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++NumSDWAPatternsFound;
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}
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break;
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}
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if (*Imm != 16 && *Imm != 24)
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case AMDGPU::V_LSHRREV_B16_e32:
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case AMDGPU::V_ASHRREV_I16_e32:
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case AMDGPU::V_LSHLREV_B16_e32: {
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// from: v_lshrrev_b16_e32 v1, 8, v0
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// to SDWA src:v0 src_sel:BYTE_1
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// from: v_ashrrev_i16_e32 v1, 8, v0
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// to SDWA src:v0 src_sel:BYTE_1 sext:1
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// from: v_lshlrev_b16_e32 v1, 8, v0
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// to SDWA dst:v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD
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MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
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auto Imm = foldToImm(*Src0);
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if (!Imm || *Imm != 8)
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break;
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MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
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MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
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if (TRI->isPhysicalRegister(Src1->getReg()) ||
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TRI->isPhysicalRegister(Dst->getReg()))
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break;
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if (Opcode == AMDGPU::V_LSHLREV_B16_e32) {
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auto SDWADst =
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make_unique<SDWADstOperand>(Dst, Src1, BYTE_1, UNUSED_PAD);
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DEBUG(dbgs() << "Match: " << MI << "To: " << *SDWADst << '\n');
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SDWAOperands[&MI] = std::move(SDWADst);
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++NumSDWAPatternsFound;
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} else {
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auto SDWASrc = make_unique<SDWASrcOperand>(
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Src1, Dst, BYTE_1, false, false,
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Opcode == AMDGPU::V_LSHRREV_B16_e32 ? false : true);
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DEBUG(dbgs() << "Match: " << MI << "To: " << *SDWASrc << '\n');
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SDWAOperands[&MI] = std::move(SDWASrc);
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++NumSDWAPatternsFound;
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}
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break;
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}
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MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
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MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
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if (TRI->isPhysicalRegister(Src1->getReg()) ||
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TRI->isPhysicalRegister(Dst->getReg()))
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break;
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case AMDGPU::V_BFE_I32:
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case AMDGPU::V_BFE_U32: {
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// e.g.:
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// from: v_bfe_u32 v1, v0, 8, 8
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// to SDWA src:v0 src_sel:BYTE_1
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// offset | width | src_sel
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// ------------------------
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// 0 | 8 | BYTE_0
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// 0 | 16 | WORD_0
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// 0 | 32 | DWORD ?
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// 8 | 8 | BYTE_1
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// 16 | 8 | BYTE_2
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// 16 | 16 | WORD_1
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// 24 | 8 | BYTE_3
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MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
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auto Offset = foldToImm(*Src1);
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if (!Offset)
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break;
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MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2);
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auto Width = foldToImm(*Src2);
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if (!Width)
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break;
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SdwaSel SrcSel = DWORD;
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if (*Offset == 0 && *Width == 8)
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SrcSel = BYTE_0;
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else if (*Offset == 0 && *Width == 16)
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SrcSel = WORD_0;
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else if (*Offset == 0 && *Width == 32)
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SrcSel = DWORD;
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else if (*Offset == 8 && *Width == 8)
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SrcSel = BYTE_1;
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else if (*Offset == 16 && *Width == 8)
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SrcSel = BYTE_2;
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else if (*Offset == 16 && *Width == 16)
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SrcSel = WORD_1;
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else if (*Offset == 24 && *Width == 8)
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SrcSel = BYTE_3;
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else
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break;
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MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
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MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
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if (TRI->isPhysicalRegister(Src0->getReg()) ||
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TRI->isPhysicalRegister(Dst->getReg()))
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break;
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if (Opcode == AMDGPU::V_LSHLREV_B32_e32) {
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auto SDWADst = make_unique<SDWADstOperand>(
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Dst, Src1, *Imm == 16 ? WORD_1 : BYTE_3, UNUSED_PAD);
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DEBUG(dbgs() << "Match: " << MI << "To: " << *SDWADst << '\n');
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SDWAOperands[&MI] = std::move(SDWADst);
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++NumSDWAPatternsFound;
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} else {
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auto SDWASrc = make_unique<SDWASrcOperand>(
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Src1, Dst, *Imm == 16 ? WORD_1 : BYTE_3, false, false,
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Opcode == AMDGPU::V_LSHRREV_B32_e32 ? false : true);
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Src0, Dst, SrcSel, false, false,
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Opcode == AMDGPU::V_BFE_U32 ? false : true);
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DEBUG(dbgs() << "Match: " << MI << "To: " << *SDWASrc << '\n');
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SDWAOperands[&MI] = std::move(SDWASrc);
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++NumSDWAPatternsFound;
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break;
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}
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break;
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}
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case AMDGPU::V_AND_B32_e32: {
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// e.g.:
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// from: v_and_b32_e32 v1, 0x0000ffff/0x000000ff, v0
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// to SDWA src:v0 src_sel:WORD_0/BYTE_0
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case AMDGPU::V_LSHRREV_B16_e32:
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case AMDGPU::V_ASHRREV_I16_e32:
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case AMDGPU::V_LSHLREV_B16_e32: {
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// from: v_lshrrev_b16_e32 v1, 8, v0
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// to SDWA src:v0 src_sel:BYTE_1
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MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
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auto Imm = foldToImm(*Src0);
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if (!Imm)
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break;
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// from: v_ashrrev_i16_e32 v1, 8, v0
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// to SDWA src:v0 src_sel:BYTE_1 sext:1
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if (*Imm != 0x0000ffff && *Imm != 0x000000ff)
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break;
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// from: v_lshlrev_b16_e32 v1, 8, v0
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// to SDWA dst:v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD
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MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
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auto Imm = foldToImm(*Src0);
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if (!Imm || *Imm != 8)
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break;
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MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
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MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
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if (TRI->isPhysicalRegister(Src1->getReg()) ||
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TRI->isPhysicalRegister(Dst->getReg()))
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break;
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MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
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MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
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if (TRI->isPhysicalRegister(Src1->getReg()) ||
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TRI->isPhysicalRegister(Dst->getReg()))
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break;
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if (Opcode == AMDGPU::V_LSHLREV_B16_e32) {
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auto SDWADst =
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make_unique<SDWADstOperand>(Dst, Src1, BYTE_1, UNUSED_PAD);
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DEBUG(dbgs() << "Match: " << MI << "To: " << *SDWADst << '\n');
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SDWAOperands[&MI] = std::move(SDWADst);
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++NumSDWAPatternsFound;
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} else {
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auto SDWASrc = make_unique<SDWASrcOperand>(
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Src1, Dst, BYTE_1, false, false,
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Opcode == AMDGPU::V_LSHRREV_B16_e32 ? false : true);
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Src1, Dst, *Imm == 0x0000ffff ? WORD_0 : BYTE_0);
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DEBUG(dbgs() << "Match: " << MI << "To: " << *SDWASrc << '\n');
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SDWAOperands[&MI] = std::move(SDWASrc);
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++NumSDWAPatternsFound;
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break;
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}
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}
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break;
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}
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case AMDGPU::V_BFE_I32:
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case AMDGPU::V_BFE_U32: {
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// e.g.:
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// from: v_bfe_u32 v1, v0, 8, 8
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// to SDWA src:v0 src_sel:BYTE_1
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// offset | width | src_sel
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// ------------------------
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// 0 | 8 | BYTE_0
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// 0 | 16 | WORD_0
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// 0 | 32 | DWORD ?
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// 8 | 8 | BYTE_1
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// 16 | 8 | BYTE_2
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// 16 | 16 | WORD_1
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// 24 | 8 | BYTE_3
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MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
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auto Offset = foldToImm(*Src1);
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if (!Offset)
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break;
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MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2);
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auto Width = foldToImm(*Src2);
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if (!Width)
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break;
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SdwaSel SrcSel = DWORD;
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if (*Offset == 0 && *Width == 8)
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SrcSel = BYTE_0;
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else if (*Offset == 0 && *Width == 16)
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SrcSel = WORD_0;
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else if (*Offset == 0 && *Width == 32)
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SrcSel = DWORD;
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else if (*Offset == 8 && *Width == 8)
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SrcSel = BYTE_1;
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else if (*Offset == 16 && *Width == 8)
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SrcSel = BYTE_2;
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else if (*Offset == 16 && *Width == 16)
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SrcSel = WORD_1;
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else if (*Offset == 24 && *Width == 8)
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SrcSel = BYTE_3;
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else
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break;
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MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
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MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
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if (TRI->isPhysicalRegister(Src0->getReg()) ||
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TRI->isPhysicalRegister(Dst->getReg()))
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break;
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auto SDWASrc = make_unique<SDWASrcOperand>(
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Src0, Dst, SrcSel, false, false,
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Opcode == AMDGPU::V_BFE_U32 ? false : true);
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DEBUG(dbgs() << "Match: " << MI << "To: " << *SDWASrc << '\n');
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SDWAOperands[&MI] = std::move(SDWASrc);
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++NumSDWAPatternsFound;
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break;
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}
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case AMDGPU::V_AND_B32_e32: {
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// e.g.:
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// from: v_and_b32_e32 v1, 0x0000ffff/0x000000ff, v0
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// to SDWA src:v0 src_sel:WORD_0/BYTE_0
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MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
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auto Imm = foldToImm(*Src0);
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if (!Imm)
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break;
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if (*Imm != 0x0000ffff && *Imm != 0x000000ff)
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break;
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MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
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MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
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if (TRI->isPhysicalRegister(Src1->getReg()) ||
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TRI->isPhysicalRegister(Dst->getReg()))
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break;
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auto SDWASrc = make_unique<SDWASrcOperand>(
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Src1, Dst, *Imm == 0x0000ffff ? WORD_0 : BYTE_0);
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DEBUG(dbgs() << "Match: " << MI << "To: " << *SDWASrc << '\n');
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SDWAOperands[&MI] = std::move(SDWASrc);
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++NumSDWAPatternsFound;
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break;
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}
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}
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}
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}
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@ -698,24 +693,21 @@ bool SIPeepholeSDWA::runOnMachineFunction(MachineFunction &MF) {
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||||
std::unordered_map<MachineInstr *, SDWAOperandsVector> PotentialMatches;
|
||||
|
||||
// FIXME: For now we only combine instructions in one basic block
|
||||
for (MachineBasicBlock &MBB : MF) {
|
||||
SDWAOperands.clear();
|
||||
matchSDWAOperands(MBB);
|
||||
matchSDWAOperands(MF);
|
||||
|
||||
PotentialMatches.clear();
|
||||
for (auto &OperandPair : SDWAOperands) {
|
||||
auto &Operand = OperandPair.second;
|
||||
MachineInstr *PotentialMI = Operand->potentialToConvert(TII);
|
||||
if (PotentialMI) {
|
||||
PotentialMatches[PotentialMI].push_back(std::move(Operand));
|
||||
}
|
||||
}
|
||||
|
||||
for (auto &PotentialPair : PotentialMatches) {
|
||||
MachineInstr &PotentialMI = *PotentialPair.first;
|
||||
convertToSDWA(PotentialMI, PotentialPair.second);
|
||||
for (auto &OperandPair : SDWAOperands) {
|
||||
auto &Operand = OperandPair.second;
|
||||
MachineInstr *PotentialMI = Operand->potentialToConvert(TII);
|
||||
if (PotentialMI) {
|
||||
PotentialMatches[PotentialMI].push_back(std::move(Operand));
|
||||
}
|
||||
}
|
||||
|
||||
for (auto &PotentialPair : PotentialMatches) {
|
||||
MachineInstr &PotentialMI = *PotentialPair.first;
|
||||
convertToSDWA(PotentialMI, PotentialPair.second);
|
||||
}
|
||||
|
||||
SDWAOperands.clear();
|
||||
return false;
|
||||
}
|
||||
|
||||
@ -376,28 +376,20 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}mul_add_shr_i32:
|
||||
; NOSDWA-NOT: v_mul_u32_u24_sdwa
|
||||
; GCN-LABEL: {{^}}add_bb_v2i16:
|
||||
; NOSDWA-NOT: v_add_i32_sdwa
|
||||
; SDWA-NOT: v_mul_u32_u24_sdwa
|
||||
; SDWA-NOT: v_add_i32_sdwa
|
||||
|
||||
define void @mul_add_shr_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %ina, i32 addrspace(1)* %inb, i1 addrspace(1)* %incond) {
|
||||
; SDWA: v_add_i32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
||||
|
||||
define amdgpu_kernel void @add_bb_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %ina, <2 x i16> addrspace(1)* %inb) {
|
||||
entry:
|
||||
%a = load i32, i32 addrspace(1)* %ina, align 4
|
||||
%b = load i32, i32 addrspace(1)* %inb, align 4
|
||||
%cond = load i1, i1 addrspace(1)* %incond, align 4
|
||||
%shra = lshr i32 %a, 16
|
||||
%shrb = lshr i32 %b, 16
|
||||
br i1 %cond, label %mul_label, label %add_label
|
||||
mul_label:
|
||||
%mul = mul i32 %shra, %shrb
|
||||
br label %store_label
|
||||
%a = load <2 x i16>, <2 x i16> addrspace(1)* %ina, align 4
|
||||
%b = load <2 x i16>, <2 x i16> addrspace(1)* %inb, align 4
|
||||
br label %add_label
|
||||
add_label:
|
||||
%add = add i32 %shra, %shrb
|
||||
%add = add <2 x i16> %a, %b
|
||||
br label %store_label
|
||||
store_label:
|
||||
%store = phi i32 [%mul, %mul_label], [%add, %add_label]
|
||||
store i32 %store, i32 addrspace(1)* %out, align 4
|
||||
store <2 x i16> %add, <2 x i16> addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user