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[ARM] Limit PerformExtractEltToVMOVRRD to when f64 is legal.

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The generic SoftFloatVectorExtract.ll test was failing when run on arm
machines, as it tries to create a f64 under soft float. Limit the
transform to when f64 is legal.

Also add a missing override, as reported in D100244.
This commit is contained in:
David Green 2021-04-20 16:24:36 +01:00
parent 51148e14d7
commit 0f24d11c47
3 changed files with 26 additions and 2 deletions
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2
lib/Target/ARM/ARMBaseRegisterInfo.h
View File

@ -213,7 +213,7 @@ public:
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
unsigned DefSubReg,
const TargetRegisterClass *SrcRC,
unsigned SrcSubReg) const;
unsigned SrcSubReg) const override;
};
} // end namespace llvm

3
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -14090,7 +14090,8 @@ PerformExtractEltToVMOVRRD(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
EVT VT = N->getValueType(0);
SDLoc dl(N);
if (!DCI.isAfterLegalizeDAG() || VT != MVT::i32)
if (!DCI.isAfterLegalizeDAG() || VT != MVT::i32 ||
!DCI.DAG.getTargetLoweringInfo().isTypeLegal(MVT::f64))
return SDValue();
SDValue Ext = SDValue(N, 0);

23
test/CodeGen/ARM/SoftFloatVectorExtract.ll Normal file
View File

@ -0,0 +1,23 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=armv7a-linux-gnu < %s | FileCheck %s
; Copied from llvm/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll,
; making sure that soft float extract works on v7a soft float triples.
@m = external global <2 x double>
define double @vector_ex() nounwind #0 {
; CHECK-LABEL: vector_ex:
; CHECK: @ %bb.0:
; CHECK-NEXT: movw r0, :lower16:m
; CHECK-NEXT: movt r0, :upper16:m
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vmov.32 r0, d17[0]
; CHECK-NEXT: vmov.32 r1, d17[1]
; CHECK-NEXT: bx lr
%v = load <2 x double>, <2 x double>* @m
%x = extractelement <2 x double> %v, i32 1
ret double %x
}
attributes #0 = { "use-soft-float" = "true" }