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[GlobalISel] Don't transform FSUB(-0, X) -> FNEG(X) in GlobalISel.

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This patch stops unconditionally transforming FSUB(-0, X) into an FNEG(X) while building the MIR.

This corresponds with the SelectionDAGISel change in D84056.

Differential Revision: https://reviews.llvm.org/D85139
This commit is contained in:
Cameron McInally 2020-08-04 11:26:04 -05:00
parent d960c0f146
commit 0f45fb4bbc
3 changed files with 7 additions and 24 deletions
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5
include/llvm/CodeGen/GlobalISel/IRTranslator.h
View File

@ -353,8 +353,6 @@ private:
/// \pre \p U is a return instruction.
bool translateRet(const User &U, MachineIRBuilder &MIRBuilder);
bool translateFSub(const User &U, MachineIRBuilder &MIRBuilder);
bool translateFNeg(const User &U, MachineIRBuilder &MIRBuilder);
bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) {
@ -439,6 +437,9 @@ private:
bool translateFAdd(const User &U, MachineIRBuilder &MIRBuilder) {
return translateBinaryOp(TargetOpcode::G_FADD, U, MIRBuilder);
}
bool translateFSub(const User &U, MachineIRBuilder &MIRBuilder) {
return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder);
}
bool translateFMul(const User &U, MachineIRBuilder &MIRBuilder) {
return translateBinaryOp(TargetOpcode::G_FMUL, U, MIRBuilder);
}

18
lib/CodeGen/GlobalISel/IRTranslator.cpp
View File

@ -294,24 +294,6 @@ bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
return true;
}
bool IRTranslator::translateFSub(const User &U, MachineIRBuilder &MIRBuilder) {
// -0.0 - X --> G_FNEG
if (isa<Constant>(U.getOperand(0)) &&
U.getOperand(0) == ConstantFP::getZeroValueForNegation(U.getType())) {
Register Op1 = getOrCreateVReg(*U.getOperand(1));
Register Res = getOrCreateVReg(U);
uint16_t Flags = 0;
if (isa<Instruction>(U)) {
const Instruction &I = cast<Instruction>(U);
Flags = MachineInstr::copyFlagsFromInstruction(I);
}
// Negate the last operand of the FSUB
MIRBuilder.buildFNeg(Res, Op1, Flags);
return true;
}
return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder);
}
bool IRTranslator::translateFNeg(const User &U, MachineIRBuilder &MIRBuilder) {
Register Op0 = getOrCreateVReg(*U.getOperand(0));
Register Res = getOrCreateVReg(U);

8
test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
View File

@ -1507,7 +1507,7 @@ define float @test_fneg_f32(float %x) {
; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FNEG [[ARG]]
; CHECK: $s0 = COPY [[RES]](s32)
%neg = fsub float -0.000000e+00, %x
%neg = fneg float %x
ret float %neg
}
@ -1516,7 +1516,7 @@ define float @test_fneg_f32_fmf(float %x) {
; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FNEG [[ARG]]
; CHECK: $s0 = COPY [[RES]](s32)
%neg = fsub fast float -0.000000e+00, %x
%neg = fneg fast float %x
ret float %neg
}
@ -1525,7 +1525,7 @@ define double @test_fneg_f64(double %x) {
; CHECK: [[ARG:%[0-9]+]]:_(s64) = COPY $d0
; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FNEG [[ARG]]
; CHECK: $d0 = COPY [[RES]](s64)
%neg = fsub double -0.000000e+00, %x
%neg = fneg double %x
ret double %neg
}
@ -1534,7 +1534,7 @@ define double @test_fneg_f64_fmf(double %x) {
; CHECK: [[ARG:%[0-9]+]]:_(s64) = COPY $d0
; CHECK: [[RES:%[0-9]+]]:_(s64) = nnan ninf nsz arcp contract afn reassoc G_FNEG [[ARG]]
; CHECK: $d0 = COPY [[RES]](s64)
%neg = fsub fast double -0.000000e+00, %x
%neg = fneg fast double %x
ret double %neg
}