RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-31 20:51:52 +01:00
Code Issues Projects Releases Wiki Activity

Add support in SplitVectorOp for remainder operators.

Browse Source 
llvm-svn: 44233
This commit is contained in:
Dan Gohman 2007-11-19 15:15:03 +00:00
parent e05d68940f
commit 0f62120b01
2 changed files with 19 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -6341,7 +6341,10 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
case ISD::FPOW: case ISD::FPOW:
case ISD::AND: case ISD::AND:
case ISD::OR: case ISD::OR:
case ISD::XOR: { case ISD::XOR:
case ISD::UREM:
case ISD::SREM:
case ISD::FREM: {
SDOperand LL, LH, RL, RH; SDOperand LL, LH, RL, RH;
SplitVectorOp(Node->getOperand(0), LL, LH); SplitVectorOp(Node->getOperand(0), LL, LH);
SplitVectorOp(Node->getOperand(1), RL, RH); SplitVectorOp(Node->getOperand(1), RL, RH);

15
test/CodeGen/X86/split-vector-rem.ll Normal file
View File

@ -0,0 +1,15 @@
; RUN: llvm-as < %s | llc -march=x86-64 | grep div | count 16
; RUN: llvm-as < %s | llc -march=x86-64 | grep fmodf | count 8
define <8 x i32> @foo(<8 x i32> %t, <8 x i32> %u) {
%m = srem <8 x i32> %t, %u
ret <8 x i32> %m
}
define <8 x i32> @bar(<8 x i32> %t, <8 x i32> %u) {
%m = urem <8 x i32> %t, %u
ret <8 x i32> %m
}
define <8 x float> @qux(<8 x float> %t, <8 x float> %u) {
%m = frem <8 x float> %t, %u
ret <8 x float> %m
}