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InstCombine: Narrow switch instructions using known bits.
Truncate the operands of a switch instruction to a narrower type if the upper bits are known to be all ones or zeros. rdar://problem/17720004 llvm-svn: 219832
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@ -2075,6 +2075,37 @@ Instruction *InstCombiner::visitBranchInst(BranchInst &BI) {
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Instruction *InstCombiner::visitSwitchInst(SwitchInst &SI) {
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Value *Cond = SI.getCondition();
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unsigned BitWidth = cast<IntegerType>(Cond->getType())->getBitWidth();
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APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
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computeKnownBits(Cond, KnownZero, KnownOne);
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unsigned LeadingKnownZeros = KnownZero.countLeadingOnes();
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unsigned LeadingKnownOnes = KnownOne.countLeadingOnes();
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// Compute the number of leading bits we can ignore.
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for (auto &C : SI.cases()) {
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LeadingKnownZeros = std::min(
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LeadingKnownZeros, C.getCaseValue()->getValue().countLeadingZeros());
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LeadingKnownOnes = std::min(
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LeadingKnownOnes, C.getCaseValue()->getValue().countLeadingOnes());
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}
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unsigned NewWidth = BitWidth - std::max(LeadingKnownZeros, LeadingKnownOnes);
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// Truncate the condition operand if the new type is equal to or larger than
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// the largest legal integer type. We need to be conservative here since
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// x86 generates redundant zero-extenstion instructions if the operand is
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// truncated to i8 or i16.
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if (BitWidth > NewWidth && NewWidth >= DL->getLargestLegalIntTypeSize()) {
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IntegerType *Ty = IntegerType::get(SI.getContext(), NewWidth);
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Builder->SetInsertPoint(&SI);
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Value *NewCond = Builder->CreateTrunc(SI.getCondition(), Ty, "trunc");
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SI.setCondition(NewCond);
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for (auto &C : SI.cases())
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static_cast<SwitchInst::CaseIt *>(&C)->setValue(
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ConstantInt::get(Ty, C.getCaseValue()->getValue().getZExtValue()));
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}
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if (Instruction *I = dyn_cast<Instruction>(Cond)) {
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if (I->getOpcode() == Instruction::Add)
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if (ConstantInt *AddRHS = dyn_cast<ConstantInt>(I->getOperand(1))) {
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61
test/Transforms/InstCombine/narrow-switch.ll
Normal file
61
test/Transforms/InstCombine/narrow-switch.ll
Normal file
@ -0,0 +1,61 @@
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; RUN: opt < %s -instcombine -S | FileCheck %s
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target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
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; CHECK-LABEL: define i32 @positive1
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; CHECK: switch i32
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; CHECK: i32 10, label
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; CHECK: i32 100, label
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; CHECK: i32 1001, label
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define i32 @positive1(i64 %a) {
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entry:
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%and = and i64 %a, 4294967295
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switch i64 %and, label %sw.default [
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i64 10, label %return
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i64 100, label %sw.bb1
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i64 1001, label %sw.bb2
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]
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sw.bb1:
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br label %return
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sw.bb2:
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br label %return
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sw.default:
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br label %return
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return:
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%retval.0 = phi i32 [ 24, %sw.default ], [ 123, %sw.bb2 ], [ 213, %sw.bb1 ], [ 231, %entry ]
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ret i32 %retval.0
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}
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; CHECK-LABEL: define i32 @negative1
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; CHECK: switch i32
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; CHECK: i32 -10, label
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; CHECK: i32 -100, label
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; CHECK: i32 -1001, label
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define i32 @negative1(i64 %a) {
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entry:
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%or = or i64 %a, -4294967296
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switch i64 %or, label %sw.default [
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i64 -10, label %return
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i64 -100, label %sw.bb1
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i64 -1001, label %sw.bb2
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]
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sw.bb1:
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br label %return
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sw.bb2:
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br label %return
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sw.default:
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br label %return
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return:
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%retval.0 = phi i32 [ 24, %sw.default ], [ 123, %sw.bb2 ], [ 213, %sw.bb1 ], [ 231, %entry ]
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ret i32 %retval.0
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}
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