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Add encodings for movement between ARM core registers and single-precision
registers. llvm-svn: 116961
This commit is contained in:
Bill Wendling
parent
369ce9c96c
commit
0f96ff63b3
@ -988,7 +988,7 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
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return;
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}
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// Set bit I(25), because this is not in immediate enconding.
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// Set bit I(25), because this is not in immediate encoding.
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Binary |= 1 << ARMII::I_BitShift;
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assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
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// Set bit[3:0] to the corresponding Rm register
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@ -51,9 +51,9 @@ def vfp_f64imm : Operand<f64>,
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//
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let canFoldAsLoad = 1, isReMaterializable = 1 in {
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def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$dst), (ins addrmode5:$addr),
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IIC_fpLoad64, "vldr", ".64\t$dst, $addr",
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[(set DPR:$dst, (f64 (load addrmode5:$addr)))]>;
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def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
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IIC_fpLoad64, "vldr", ".64\t$Dd, $addr",
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[(set DPR:$Dd, (f64 (load addrmode5:$addr)))]>;
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def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr),
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IIC_fpLoad32, "vldr", ".32\t$dst, $addr",
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@ -469,13 +469,39 @@ def VMOVS : ASuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
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// FP <-> GPR Copies. Int <-> FP Conversions.
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//
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def VMOVRS : AVConv2I<0b11100001, 0b1010, (outs GPR:$dst), (ins SPR:$src),
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IIC_fpMOVSI, "vmov", "\t$dst, $src",
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[(set GPR:$dst, (bitconvert SPR:$src))]>;
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def VMOVRS : AVConv2I<0b11100001, 0b1010,
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(outs GPR:$Rt), (ins SPR:$Sn),
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IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
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[(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
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// Instruction operands.
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bits<4> Rt;
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bits<5> Sn;
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def VMOVSR : AVConv4I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:$src),
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IIC_fpMOVIS, "vmov", "\t$dst, $src",
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[(set SPR:$dst, (bitconvert GPR:$src))]>;
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// Encode instruction operands.
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let Inst{19-16} = Sn{4-1};
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let Inst{7} = Sn{0};
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let Inst{15-12} = Rt;
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let Inst{6-5} = 0b00;
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let Inst{3-0} = 0b0000;
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}
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def VMOVSR : AVConv4I<0b11100000, 0b1010,
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(outs SPR:$Sn), (ins GPR:$Rt),
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IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
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[(set SPR:$Sn, (bitconvert GPR:$Rt))]> {
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// Instruction operands.
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bits<5> Sn;
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bits<4> Rt;
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// Encode instruction operands.
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let Inst{19-16} = Sn{4-1};
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let Inst{7} = Sn{0};
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let Inst{15-12} = Rt;
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let Inst{6-5} = 0b00;
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let Inst{3-0} = 0b0000;
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}
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let neverHasSideEffects = 1 in {
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def VMOVRRD : AVConv3I<0b11000101, 0b1011,
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@ -883,29 +909,29 @@ def : Pat<(fsub (fmul SPR:$a, SPR:$b), SPR:$dstin),
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//
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let neverHasSideEffects = 1 in {
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def VMOVDcc : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
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(outs DPR:$dst), (ins DPR:$false, DPR:$true),
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IIC_fpUNA64, "vmov", ".f64\t$dst, $true",
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[/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))*/]>,
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RegConstraint<"$false = $dst">;
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def VMOVDcc : ADuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
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(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
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IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm",
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[/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>,
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RegConstraint<"$Dn = $Dd">;
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def VMOVScc : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
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(outs SPR:$dst), (ins SPR:$false, SPR:$true),
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IIC_fpUNA32, "vmov", ".f32\t$dst, $true",
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[/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))*/]>,
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RegConstraint<"$false = $dst">;
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def VMOVScc : ASuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
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(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
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IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm",
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[/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>,
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RegConstraint<"$Sn = $Sd">;
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def VNEGDcc : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
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(outs DPR:$dst), (ins DPR:$false, DPR:$true),
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IIC_fpUNA64, "vneg", ".f64\t$dst, $true",
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[/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))*/]>,
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RegConstraint<"$false = $dst">;
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def VNEGDcc : ADuI_Encode<0b11101, 0b11, 0b0001, 0b01, 0,
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(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
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IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
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[/*(set DPR:$Dd, (ARMcneg DPR:$Dn, DPR:$Dm, imm:$cc))*/]>,
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RegConstraint<"$Dn = $Dd">;
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def VNEGScc : ASuI<0b11101, 0b11, 0b0001, 0b01, 0,
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(outs SPR:$dst), (ins SPR:$false, SPR:$true),
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IIC_fpUNA32, "vneg", ".f32\t$dst, $true",
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[/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))*/]>,
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RegConstraint<"$false = $dst">;
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def VNEGScc : ASuI_Encode<0b11101, 0b11, 0b0001, 0b01, 0,
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(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
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IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
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[/*(set SPR:$Sd, (ARMcneg SPR:$Sn, SPR:$Sm, imm:$cc))*/]>,
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RegConstraint<"$Sn = $Sd">;
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} // neverHasSideEffects
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//===----------------------------------------------------------------------===//
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@ -1,4 +1,4 @@
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;RUN: llc -mtriple=armv7-apple-darwin -mcpu=cortex-a8 -mattr=-neonfp -show-mc-encoding < %s | FileCheck %s
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; RUN: llc -mtriple=armv7-apple-darwin -mcpu=cortex-a8 -mattr=-neonfp -show-mc-encoding < %s | FileCheck %s
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; FIXME: Once the ARM integrated assembler is up and going, these sorts of tests
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@ -275,27 +275,27 @@ entry:
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ret float %add
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}
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define double @f94(double %a, double %b, double %c) nounwind readnone {
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define double @f92(double %a, double %b, double %c) nounwind readnone {
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entry:
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; CHECK: f94
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; CHECK: f92
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; CHECK: vmls.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x42,0xee]
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%mul = fmul double %a, %b
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%sub = fsub double %c, %mul
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ret double %sub
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}
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define float @f95(float %a, float %b, float %c) nounwind readnone {
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define float @f93(float %a, float %b, float %c) nounwind readnone {
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entry:
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; CHECK: f95
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; CHECK: f93
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; CHECK: vmls.f32 s2, s1, s0 @ encoding: [0xc0,0x1a,0x00,0xee]
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%mul = fmul float %a, %b
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%sub = fsub float %c, %mul
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ret float %sub
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}
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define double @f96(double %a, double %b, double %c) nounwind readnone {
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define double @f94(double %a, double %b, double %c) nounwind readnone {
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entry:
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; CHECK: f96
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; CHECK: f94
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; CHECK: vnmla.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x52,0xee]
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%mul = fmul double %a, %b
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%sub = fsub double -0.000000e+00, %mul
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@ -303,9 +303,9 @@ entry:
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ret double %sub3
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}
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define float @f97(float %a, float %b, float %c) nounwind readnone {
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define float @f95(float %a, float %b, float %c) nounwind readnone {
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entry:
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; CHECK: f97
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; CHECK: f95
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; CHECK: vnmla.f32 s2, s1, s0 @ encoding: [0xc0,0x1a,0x10,0xee]
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%mul = fmul float %a, %b
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%sub = fsub float -0.000000e+00, %mul
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@ -313,18 +313,18 @@ entry:
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ret float %sub3
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}
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define double @f92(double %a, double %b, double %c) nounwind readnone {
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define double @f96(double %a, double %b, double %c) nounwind readnone {
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entry:
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; CHECK: f92
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; CHECK: f96
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; CHECK: vnmls.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x52,0xee]
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%mul = fmul double %a, %b
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%sub = fsub double %mul, %c
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ret double %sub
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}
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define float @f93(float %a, float %b, float %c) nounwind readnone {
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define float @f97(float %a, float %b, float %c) nounwind readnone {
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entry:
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; CHECK: f93
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; CHECK: f97
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; CHECK: vnmls.f32 s2, s1, s0 @ encoding: [0x80,0x1a,0x10,0xee]
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%mul = fmul float %a, %b
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%sub = fsub float %mul, %c
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@ -333,6 +333,38 @@ entry:
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; FIXME: Check for fmstat instruction.
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define double @f98(double %a, i32 %i) nounwind readnone {
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entry:
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%cmp = icmp eq i32 %i, 3
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br i1 %cmp, label %return, label %if.end
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if.end: ; preds = %entry
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; CHECK: f98
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; CHECK: vnegne.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0x1e]
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%sub = fsub double -0.000000e+00, %a
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ret double %sub
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return: ; preds = %entry
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ret double %a
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}
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define float @f99(float %a, i32 %i) nounwind readnone {
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entry:
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%cmp = icmp eq i32 %i, 3
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br i1 %cmp, label %if.end, label %return
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if.end: ; preds = %entry
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; CHECK: f99
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; CHECK: vmovne r0, s0 @ encoding: [0x10,0x0a,0x10,0x1e]
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%sub = fsub float -0.000000e+00, %a
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ret float %sub
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return: ; preds = %entry
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ret float %a
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}
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define i32 @f100() nounwind readnone {
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entry:
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; CHECK: f100
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@ -368,3 +400,26 @@ entry:
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%add = fadd float %a, 3.000000e+00
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ret float %add
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}
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define void @f104(float %a, float %b, float %c, float %d, float %e, float %f) nounwind {
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entry:
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; CHECK: f104
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; CHECK: vmov s2, r0 @ encoding: [0x10,0x0a,0x01,0xee]
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; CHECK: vmov s3, r1 @ encoding: [0x90,0x1a,0x01,0xee]
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; CHECK: vmov s4, r2 @ encoding: [0x10,0x2a,0x02,0xee]
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; CHECK: vmov s5, r3 @ encoding: [0x90,0x3a,0x02,0xee]
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%conv = fptosi float %a to i32
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%conv2 = fptosi float %b to i32
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%conv4 = fptosi float %c to i32
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%conv6 = fptosi float %d to i32
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%conv8 = fptosi float %e to i32
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%conv10 = fptosi float %f to i32
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tail call void @g104(i32 %conv, i32 %conv2, i32 %conv4, i32 %conv6, i32 %conv8, i32 %conv10) nounwind
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; CHECK: vmov r0, s2 @ encoding: [0x10,0x0a,0x11,0xee]
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; CHECK: vmov r1, s3 @ encoding: [0x90,0x1a,0x11,0xee]
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; CHECK: vmov r2, s4 @ encoding: [0x10,0x2a,0x12,0xee]
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; CHECK: vmov r3, s5 @ encoding: [0x90,0x3a,0x12,0xee]
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ret void
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}
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declare void @g104(i32, i32, i32, i32, i32, i32)
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