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R600/SI: Add a calling convention for compute shaders
llvm-svn: 183137
This commit is contained in:
Tom Stellard
parent
47a52f3e69
commit
0faf53682e
@ -32,17 +32,21 @@ def CC_SI : CallingConv<[
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VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
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VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
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VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31
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]>>>,
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]>>>
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// This is the default for i64 values.
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// XXX: We should change this once clang understands the CC_AMDGPU.
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CCIfType<[i64], CCAssignToRegWithShadow<
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[ SGPR0, SGPR2, SGPR4, SGPR6, SGPR8, SGPR10, SGPR12, SGPR14 ],
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[ SGPR1, SGPR3, SGPR5, SGPR7, SGPR9, SGPR11, SGPR13, SGPR15 ]
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>>
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]>;
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// Calling convention for SI compute kernels
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def CC_SI_Kernel : CallingConv<[
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CCIfType<[i64], CCAssignToStack <8, 4>>,
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CCIfType<[i32, f32], CCAssignToStack <4, 4>>,
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CCIfType<[i16], CCAssignToStack <2, 4>>,
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CCIfType<[i8], CCAssignToStack <1, 4>>
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]>;
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def CC_AMDGPU : CallingConv<[
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CCIf<"State.getMachineFunction().getInfo<SIMachineFunctionInfo>()->"#
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"ShaderType == ShaderType::COMPUTE", CCDelegateTo<CC_SI_Kernel>>,
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CCIf<"State.getTarget().getSubtarget<AMDGPUSubtarget>().device()"#
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"->getGeneration() == AMDGPUDeviceInfo::HD7XXX", CCDelegateTo<CC_SI>>
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]>;
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@ -14,9 +14,11 @@
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//===----------------------------------------------------------------------===//
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#include "AMDGPUISelLowering.h"
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#include "AMDGPU.h"
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#include "AMDGPURegisterInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "AMDILIntrinsicInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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@ -121,7 +121,7 @@ SDValue SITargetLowering::LowerFormalArguments(
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}
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// Second split vertices into their elements
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if (Arg.VT.isVector()) {
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if (Info->ShaderType != ShaderType::COMPUTE && Arg.VT.isVector()) {
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ISD::InputArg NewArg = Arg;
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NewArg.Flags.setSplit();
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NewArg.VT = Arg.VT.getVectorElementType();
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@ -153,6 +153,14 @@ SDValue SITargetLowering::LowerFormalArguments(
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CCInfo.AllocateReg(AMDGPU::VGPR1);
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}
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unsigned ArgReg = 0;
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// The pointer to the list of arguments is stored in SGPR0, SGPR1
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if (Info->ShaderType == ShaderType::COMPUTE) {
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CCInfo.AllocateReg(AMDGPU::SGPR0);
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CCInfo.AllocateReg(AMDGPU::SGPR1);
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ArgReg = MF.addLiveIn(AMDGPU::SGPR0_SGPR1, &AMDGPU::SReg_64RegClass);
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}
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AnalyzeFormalArguments(CCInfo, Splits);
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for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
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@ -164,10 +172,26 @@ SDValue SITargetLowering::LowerFormalArguments(
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}
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CCValAssign &VA = ArgLocs[ArgIdx++];
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EVT VT = VA.getLocVT();
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if (VA.isMemLoc()) {
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assert(ArgReg);
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PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
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AMDGPUAS::CONSTANT_ADDRESS);
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EVT ArgVT = MVT::getIntegerVT(VT.getSizeInBits());
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SDValue BasePtr = DAG.getCopyFromReg(DAG.getRoot(), DL,
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ArgReg, MVT::i64);
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SDValue Ptr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
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DAG.getConstant(VA.getLocMemOffset(), MVT::i64));
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SDValue Arg = DAG.getExtLoad(ISD::ZEXTLOAD, DL, VT, DAG.getRoot(), Ptr,
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MachinePointerInfo(UndefValue::get(PtrTy)),
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VA.getValVT(), false, false, ArgVT.getSizeInBits() >> 3);
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InVals.push_back(Arg);
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continue;
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}
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assert(VA.isRegLoc() && "Parameter must be in a register!");
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unsigned Reg = VA.getLocReg();
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MVT VT = VA.getLocVT();
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if (VT == MVT::i64) {
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// For now assume it is a pointer
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@ -38,8 +38,8 @@ entry:
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; R600-CHECK: @bfi_sha256_ma
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; R600-CHECK: XOR_INT * [[DST:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-CHECK: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]|PV\.[XYZW]}}, {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI-CHECK: V_XOR_B32_e32 [[DST:VGPR[0-9]+]], {{VGPR[0-9]+, VGPR[0-9]+}}
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; SI-CHECK: V_BFI_B32 {{VGPR[0-9]+}}, [[DST]], {{VGPR[0-9]+, VGPR[0-9]+}}
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; SI-CHECK: V_XOR_B32_e64 [[DST:VGPR[0-9]+]], {{[SV]GPR[0-9]+, [SV]GPR[0-9]+}}
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; SI-CHECK: V_BFI_B32 {{VGPR[0-9]+}}, [[DST]], {{[SV]GPR[0-9]+, [SV]GPR[0-9]+}}
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define void @bfi_sha256_ma(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
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entry:
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@ -1,6 +1,6 @@
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;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
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;CHECK: V_LSHLREV_B32_e32 VGPR0, 1, VGPR0
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;CHECK: V_LSHL_B32_e64 VGPR{{[0-9]+}}, {{[SV]GPR[0-9]+}}, 1
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define void @test(i32 %p) {
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%i = mul i32 %p, 2
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@ -1,6 +1,6 @@
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;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
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;CHECK: V_LSHRREV_B32_e32 VGPR0, 1, VGPR0
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;CHECK: V_LSHR_B32_e64 {{VGPR[0-9]+}}, {{[SV]GPR[0-9]+}}, 1
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define void @test(i32 %p) {
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%i = udiv i32 %p, 2
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@ -1,7 +1,7 @@
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;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
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;CHECK: V_MOV_B32_e32 VGPR1, -1431655765
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;CHECK-NEXT: V_MUL_HI_U32 VGPR0, VGPR0, VGPR1, 0, 0, 0, 0, 0
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;CHECK: V_MOV_B32_e32 VGPR{{[0-9]+}}, -1431655765
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;CHECK: V_MUL_HI_U32 VGPR0, {{[SV]GPR[0-9]+}}, {{VGPR[0-9]+}}
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;CHECK-NEXT: V_LSHRREV_B32_e32 VGPR0, 1, VGPR0
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define void @test(i32 %p) {
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@ -22,8 +22,8 @@ entry:
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; R600-CHECK: BIT_ALIGN_INT {{\** T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PV.[XYZW]}}
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; SI-CHECK: @rotl
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; SI-CHECK: V_SUB_I32_e32 [[DST:VGPR[0-9]+]], 32, {{VGPR[0-9]+}}
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; SI-CHECK: V_ALIGNBIT_B32 {{VGPR[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}, [[DST]]
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; SI-CHECK: V_SUB_I32_e64 [[DST:VGPR[0-9]+]], 32, {{[SV]GPR[0-9]+}}
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; SI-CHECK: V_ALIGNBIT_B32 {{VGPR[0-9]+, [SV]GPR[0-9]+, VGPR[0-9]+}}, [[DST]]
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define void @rotl(i32 addrspace(1)* %in, i32 %x, i32 %y) {
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entry:
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%0 = shl i32 %x, %y
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@ -1,6 +1,6 @@
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;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
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;CHECK: V_CMP_O_F32_e64 SGPR0_SGPR1, VGPR0, VGPR0, 0, 0, 0, 0
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;CHECK: V_CMP_O_F32_e64 SGPR0_SGPR1, {{[SV]GPR[0-9]+, [SV]GPR[0-9]+}}, 0, 0, 0, 0
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define void @main(float %p) {
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main_body:
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@ -1,6 +1,6 @@
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;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
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;CHECK: V_CMP_U_F32_e64 SGPR0_SGPR1, VGPR0, VGPR0, 0, 0, 0, 0
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;CHECK: V_CMP_U_F32_e64 SGPR0_SGPR1, {{[SV]GPR[0-9]+, [SV]GPR[0-9]+}}, 0, 0, 0, 0
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define void @main(float %p) {
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main_body:
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