From 0fd61ed25a043d7533d601a8cc67442c0ad3a38a Mon Sep 17 00:00:00 2001 From: Anton Korobeynikov Date: Thu, 16 Jul 2009 14:03:41 +0000 Subject: [PATCH] 32-bit ri addressing mode has only 12-bit displacement llvm-svn: 75973 --- lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | 84 ++++++++++++++++++++++ lib/Target/SystemZ/SystemZInstrInfo.td | 22 ++++-- 2 files changed, 101 insertions(+), 5 deletions(-) diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index 3e1cc3c544d..603cfecb594 100644 --- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -105,6 +105,8 @@ namespace { #include "SystemZGenDAGISel.inc" private: + bool SelectAddrRI32(const SDValue& Op, SDValue& Addr, + SDValue &Base, SDValue &Disp); bool SelectAddrRI(const SDValue& Op, SDValue& Addr, SDValue &Base, SDValue &Disp); bool SelectAddrRRI(SDValue Op, SDValue Addr, @@ -153,6 +155,88 @@ static bool isImmSExt20(SDValue Op, int64_t &Imm) { return isImmSExt20(Op.getNode(), Imm); } +/// isImmSExt12 - This method tests to see if the node is either a 32-bit +/// or 64-bit immediate, and if the value can be accurately represented as a +/// zero extension from a 12-bit value. If so, this returns true and the +/// immediate. +static bool isImmZExt12(SDNode *N, uint64_t &Imm) { + if (N->getOpcode() != ISD::Constant) + return false; + + uint64_t Val = cast(N)->getZExtValue(); + if (Val <= 0xFFF) { + Imm = Val; + return true; + } + + return false; +} + +static bool isImmZExt12(SDValue Op, uint64_t &Imm) { + return isImmZExt12(Op.getNode(), Imm); +} + +/// Returns true if the address can be represented by a base register plus +/// an unsigned 12-bit displacement [r+imm]. +bool SystemZDAGToDAGISel::SelectAddrRI32(const SDValue& Op, SDValue& Addr, + SDValue &Base, SDValue &Disp) { + // FIXME dl should come from parent load or store, not from address + DebugLoc dl = Addr.getDebugLoc(); + MVT VT = Addr.getValueType(); + + if (Addr.getOpcode() == ISD::ADD) { + uint64_t Imm = 0; + if (isImmZExt12(Addr.getOperand(1), Imm)) { + Disp = CurDAG->getTargetConstant(Imm, MVT::i64); + if (FrameIndexSDNode *FI = + dyn_cast(Addr.getOperand(0))) { + Base = CurDAG->getTargetFrameIndex(FI->getIndex(), VT); + } else { + Base = Addr.getOperand(0); + } + return true; // [r+i] + } + } else if (Addr.getOpcode() == ISD::OR) { + uint64_t Imm = 0; + if (isImmZExt12(Addr.getOperand(1), Imm)) { + // If this is an or of disjoint bitfields, we can codegen this as an add + // (for better address arithmetic) if the LHS and RHS of the OR are + // provably disjoint. + APInt LHSKnownZero, LHSKnownOne; + CurDAG->ComputeMaskedBits(Addr.getOperand(0), + APInt::getAllOnesValue(Addr.getOperand(0) + .getValueSizeInBits()), + LHSKnownZero, LHSKnownOne); + + if ((LHSKnownZero.getZExtValue()|~(uint64_t)Imm) == ~0ULL) { + // If all of the bits are known zero on the LHS or RHS, the add won't + // carry. + Base = Addr.getOperand(0); + Disp = CurDAG->getTargetConstant(Imm, MVT::i64); + return true; + } + } + } else if (ConstantSDNode *CN = dyn_cast(Addr)) { + // Loading from a constant address. + + // If this address fits entirely in a 12-bit zext immediate field, codegen + // this as "d(r0)" + uint64_t Imm; + if (isImmZExt12(CN, Imm)) { + Disp = CurDAG->getTargetConstant(Imm, MVT::i64); + Base = CurDAG->getRegister(0, VT); + return true; + } + } + + Disp = CurDAG->getTargetConstant(0, MVT::i64); + if (FrameIndexSDNode *FI = dyn_cast(Addr)) + Base = CurDAG->getTargetFrameIndex(FI->getIndex(), VT); + else + Base = Addr; + return true; // [r+0] +} + /// Returns true if the address can be represented by a base register plus /// a signed 20-bit displacement [r+imm]. bool SystemZDAGToDAGISel::SelectAddrRI(const SDValue& Op, SDValue& Addr, diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index ec0956e48ec..2c08c2fe601 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -205,6 +205,11 @@ def i32i16imm : Operand; def i64i32imm : Operand; // Branch targets have OtherVT type. def brtarget : Operand; + +// Unigned i12 +def u12imm : Operand { + let PrintMethod = "printU16ImmOperand"; +} // Signed i16 def s16imm : Operand { let PrintMethod = "printS16ImmOperand"; @@ -212,6 +217,13 @@ def s16imm : Operand { def s16imm64 : Operand { let PrintMethod = "printS16ImmOperand"; } +// Signed i20 +def s20imm : Operand { + let PrintMethod = "printS20ImmOperand"; +} +def s20imm64 : Operand { + let PrintMethod = "printS20ImmOperand"; +} // Signed i32 def s32imm : Operand { let PrintMethod = "printS32ImmOperand"; @@ -228,15 +240,15 @@ def s32imm64 : Operand { // riaddr := reg + imm def riaddr32 : Operand, - ComplexPattern { + ComplexPattern { let PrintMethod = "printRIAddrOperand"; - let MIOperandInfo = (ops ADDR32:$base, i32imm:$disp); + let MIOperandInfo = (ops ADDR32:$base, u12imm:$disp); } def riaddr : Operand, ComplexPattern { let PrintMethod = "printRIAddrOperand"; - let MIOperandInfo = (ops ADDR64:$base, i64imm:$disp); + let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp); } //===----------------------------------------------------------------------===// @@ -245,12 +257,12 @@ def riaddr : Operand, def rriaddr : Operand, ComplexPattern { let PrintMethod = "printRRIAddrOperand"; - let MIOperandInfo = (ops ADDR64:$base, i64imm:$disp, ADDR64:$index); + let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp, ADDR64:$index); } def laaddr : Operand, ComplexPattern { let PrintMethod = "printRRIAddrOperand"; - let MIOperandInfo = (ops ADDR64:$base, i64imm:$disp, ADDR64:$index); + let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp, ADDR64:$index); } //===----------------------------------------------------------------------===//