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Refactor MipsTargetLowering::EmitInstrWithCustomInserter.
llvm-svn: 132726
This commit is contained in:
Akira Hatanaka
parent
e56d1fa083
commit
101d50423a
@ -554,16 +554,108 @@ static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
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return Mips::BRANCH_INVALID;
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}
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static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
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DebugLoc dl,
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const MipsSubtarget* Subtarget,
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const TargetInstrInfo *TII,
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bool isFPCmp, unsigned Opc) {
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// There is no need to expand CMov instructions if target has
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// conditional moves.
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if (Subtarget->hasCondMov())
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return BB;
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// To "insert" a SELECT_CC instruction, we actually have to insert the
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// diamond control-flow pattern. The incoming instruction knows the
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// destination vreg to set, the condition code register to branch on, the
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// true/false values to select between, and a branch opcode to use.
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction::iterator It = BB;
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++It;
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// thisMBB:
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// ...
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// TrueVal = ...
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// setcc r1, r2, r3
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// bNE r1, r0, copy1MBB
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// fallthrough --> copy0MBB
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MachineBasicBlock *thisMBB = BB;
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MachineFunction *F = BB->getParent();
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MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
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F->insert(It, copy0MBB);
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F->insert(It, sinkMBB);
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// Transfer the remainder of BB and its successor edges to sinkMBB.
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sinkMBB->splice(sinkMBB->begin(), BB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
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// Next, add the true and fallthrough blocks as its successors.
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BB->addSuccessor(copy0MBB);
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BB->addSuccessor(sinkMBB);
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// Emit the right instruction according to the type of the operands compared
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if (isFPCmp)
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BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
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else
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BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
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.addReg(Mips::ZERO).addMBB(sinkMBB);
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// copy0MBB:
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// %FalseValue = ...
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// # fallthrough to sinkMBB
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BB = copy0MBB;
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// Update machine-CFG edges
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BB->addSuccessor(sinkMBB);
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// sinkMBB:
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// %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
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// ...
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BB = sinkMBB;
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if (isFPCmp)
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BuildMI(*BB, BB->begin(), dl,
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TII->get(Mips::PHI), MI->getOperand(0).getReg())
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.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
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.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
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else
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BuildMI(*BB, BB->begin(), dl,
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TII->get(Mips::PHI), MI->getOperand(0).getReg())
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.addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
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.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
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MI->eraseFromParent(); // The pseudo instruction is gone now.
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return BB;
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}
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MachineBasicBlock *
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MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB) const {
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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bool isFPCmp = false;
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DebugLoc dl = MI->getDebugLoc();
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unsigned Opc;
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switch (MI->getOpcode()) {
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default: assert(false && "Unexpected instr type to insert");
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default:
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assert(false && "Unexpected instr type to insert");
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return NULL;
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case Mips::MOVT:
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case Mips::MOVT_S:
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case Mips::MOVT_D:
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return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1F);
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case Mips::MOVF:
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case Mips::MOVF_S:
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case Mips::MOVF_D:
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return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1T);
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case Mips::MOVZ_I:
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case Mips::MOVZ_S:
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case Mips::MOVZ_D:
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return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BNE);
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case Mips::MOVN_I:
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case Mips::MOVN_S:
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case Mips::MOVN_D:
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return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BEQ);
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case Mips::ATOMIC_LOAD_ADD_I8:
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return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
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@ -620,101 +712,7 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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return EmitAtomicCmpSwapPartword(MI, BB, 2);
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case Mips::ATOMIC_CMP_SWAP_I32:
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return EmitAtomicCmpSwap(MI, BB, 4);
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case Mips::MOVT:
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case Mips::MOVT_S:
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case Mips::MOVT_D:
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isFPCmp = true;
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Opc = Mips::BC1F;
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break;
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case Mips::MOVF:
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case Mips::MOVF_S:
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case Mips::MOVF_D:
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isFPCmp = true;
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Opc = Mips::BC1T;
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break;
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case Mips::MOVZ_I:
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case Mips::MOVZ_S:
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case Mips::MOVZ_D:
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Opc = Mips::BNE;
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break;
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case Mips::MOVN_I:
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case Mips::MOVN_S:
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case Mips::MOVN_D:
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Opc = Mips::BEQ;
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break;
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}
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// There is no need to expand CMov instructions if target has
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// conditional moves.
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if (Subtarget->hasCondMov())
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return BB;
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// To "insert" a SELECT_CC instruction, we actually have to insert the
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// diamond control-flow pattern. The incoming instruction knows the
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// destination vreg to set, the condition code register to branch on, the
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// true/false values to select between, and a branch opcode to use.
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction::iterator It = BB;
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++It;
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// thisMBB:
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// ...
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// TrueVal = ...
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// setcc r1, r2, r3
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// bNE r1, r0, copy1MBB
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// fallthrough --> copy0MBB
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MachineBasicBlock *thisMBB = BB;
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MachineFunction *F = BB->getParent();
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MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
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F->insert(It, copy0MBB);
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F->insert(It, sinkMBB);
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// Transfer the remainder of BB and its successor edges to sinkMBB.
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sinkMBB->splice(sinkMBB->begin(), BB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
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// Next, add the true and fallthrough blocks as its successors.
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BB->addSuccessor(copy0MBB);
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BB->addSuccessor(sinkMBB);
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// Emit the right instruction according to the type of the operands compared
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if (isFPCmp)
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BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
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else
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BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
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.addReg(Mips::ZERO).addMBB(sinkMBB);
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// copy0MBB:
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// %FalseValue = ...
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// # fallthrough to sinkMBB
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BB = copy0MBB;
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// Update machine-CFG edges
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BB->addSuccessor(sinkMBB);
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// sinkMBB:
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// %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
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// ...
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BB = sinkMBB;
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if (isFPCmp)
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BuildMI(*BB, BB->begin(), dl,
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TII->get(Mips::PHI), MI->getOperand(0).getReg())
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.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
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.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
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else
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BuildMI(*BB, BB->begin(), dl,
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TII->get(Mips::PHI), MI->getOperand(0).getReg())
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.addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
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.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
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MI->eraseFromParent(); // The pseudo instruction is gone now.
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return BB;
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}
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// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
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