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[CGP] Ensure address scaled offset is representable as int64_t
AddressingModeMatcher::matchScaledValue was calling getSExtValue for a constant before ensuring that we can actually represent the value as int64_t Fixes OSSFuzz#22723 which is a followup to rGc479052a74b2 (PR46004 / OSSFuzz#22357)
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@ -3715,10 +3715,11 @@ bool AddressingModeMatcher::matchScaledValue(Value *ScaleReg, int64_t Scale,
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// X*Scale + C*Scale to addr mode.
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ConstantInt *CI = nullptr; Value *AddLHS = nullptr;
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if (isa<Instruction>(ScaleReg) && // not a constant expr.
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match(ScaleReg, m_Add(m_Value(AddLHS), m_ConstantInt(CI)))) {
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match(ScaleReg, m_Add(m_Value(AddLHS), m_ConstantInt(CI))) &&
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CI->getValue().isSignedIntN(64)) {
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TestAddrMode.InBounds = false;
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TestAddrMode.ScaledReg = AddLHS;
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TestAddrMode.BaseOffs += CI->getSExtValue()*TestAddrMode.Scale;
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TestAddrMode.BaseOffs += CI->getSExtValue() * TestAddrMode.Scale;
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// If this addressing mode is legal, commit it and remember that we folded
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// this instruction.
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@ -19,3 +19,18 @@ define void @fuzz22357(i128 %a0) {
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store i8 0, i8* %3, align 1
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ret void
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}
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; OSS Fuzz: https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=22723
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define void @fuzz22723(i128 %a0) {
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; X86-LABEL: fuzz22723:
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; X86: # %bb.0:
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; X86-NEXT: retl
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;
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; X64-LABEL: fuzz22723:
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; X64: # %bb.0:
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; X64-NEXT: retq
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%1 = add i128 %a0, 170141183460469231731687303715884105727
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%2 = getelementptr i128*, i128** undef, i128 %1
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store i128* undef, i128** %2, align 8
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ret void
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}
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