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https://github.com/RPCS3/llvm-mirror.git
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Recommit "[X86] Remove XOP VPCMOV intrinsics and autoupgrade them to native IR."
Clang has now been fixed to not use these intrinsics. llvm-svn: 295571
This commit is contained in:
Craig Topper
parent
e664e4e1d9
commit
109be6a74d
@ -3033,17 +3033,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_xop_vfrcz_ps_256 : GCCBuiltin<"__builtin_ia32_vfrczps256">,
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Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty], [IntrNoMem]>;
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def int_x86_xop_vpcmov :
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GCCBuiltin<"__builtin_ia32_vpcmov">,
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Intrinsic<[llvm_v2i64_ty],
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[llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty],
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[IntrNoMem]>;
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def int_x86_xop_vpcmov_256 :
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GCCBuiltin<"__builtin_ia32_vpcmov_256">,
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Intrinsic<[llvm_v4i64_ty],
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[llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty],
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[IntrNoMem]>;
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def int_x86_xop_vpcomb : GCCBuiltin<"__builtin_ia32_vpcomb">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty,
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llvm_i8_ty], [IntrNoMem]>;
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@ -230,7 +230,7 @@ static bool ShouldUpgradeX86Intrinsic(Function *F, StringRef Name) {
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Name.startswith("avx2.pblendd.") || // Added in 3.7
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Name.startswith("avx.vbroadcastf128") || // Added in 4.0
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Name == "avx2.vbroadcasti128" || // Added in 3.7
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Name == "xop.vpcmov" || // Added in 3.8
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Name.startswith("xop.vpcmov") || // Added in 3.8
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Name.startswith("avx512.mask.move.s") || // Added in 4.0
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(Name.startswith("xop.vpcom") && // Added in 3.2
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F->arg_size() == 2))
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@ -1078,7 +1078,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
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Rep =
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Builder.CreateCall(VPCOM, {CI->getArgOperand(0), CI->getArgOperand(1),
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Builder.getInt8(Imm)});
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} else if (IsX86 && Name == "xop.vpcmov") {
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} else if (IsX86 && Name.startswith("xop.vpcmov")) {
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Value *Sel = CI->getArgOperand(2);
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Value *NotSel = Builder.CreateNot(Sel);
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Value *Sel0 = Builder.CreateAnd(CI->getArgOperand(0), Sel);
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@ -1777,7 +1777,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
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// XOP foldable instructions
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{ X86::VPCMOVrrr, X86::VPCMOVrmr, 0 },
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{ X86::VPCMOVrrrY, X86::VPCMOVrmrY, 0 },
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{ X86::VPCMOVYrrr, X86::VPCMOVYrmr, 0 },
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{ X86::VPCOMBri, X86::VPCOMBmi, 0 },
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{ X86::VPCOMDri, X86::VPCOMDmi, 0 },
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{ X86::VPCOMQri, X86::VPCOMQmi, 0 },
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@ -2478,7 +2478,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
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// XOP foldable instructions
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{ X86::VPCMOVrrr, X86::VPCMOVrrm, 0 },
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{ X86::VPCMOVrrrY, X86::VPCMOVrrmY, 0 },
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{ X86::VPCMOVYrrr, X86::VPCMOVYrrm, 0 },
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{ X86::VPERMIL2PDrr, X86::VPERMIL2PDrm, 0 },
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{ X86::VPERMIL2PDrrY, X86::VPERMIL2PDrmY, 0 },
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{ X86::VPERMIL2PSrr, X86::VPERMIL2PSrm, 0 },
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@ -290,84 +290,41 @@ let ExeDomain = SSEPackedInt in {
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}
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// Instruction where either second or third source can be memory
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multiclass xop4op_int<bits<8> opc, string OpcodeStr,
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Intrinsic Int128, Intrinsic Int256> {
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multiclass xop4op_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
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X86MemOperand x86memop, ValueType VT> {
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// 128-bit Instruction
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def rrr : IXOPi8Reg<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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def rrr : IXOPi8Reg<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2, VR128:$src3))]>,
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XOP_4V;
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def rrm : IXOPi8Reg<opc, MRMSrcMemOp4, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i128mem:$src3),
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[(set RC:$dst, (VT (or (and RC:$src3, RC:$src1),
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(X86andnp RC:$src3, RC:$src2))))]>, XOP_4V;
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def rrm : IXOPi8Reg<opc, MRMSrcMemOp4, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, x86memop:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(Int128 VR128:$src1, VR128:$src2,
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(bitconvert (loadv2i64 addr:$src3))))]>,
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[(set RC:$dst, (VT (or (and (load addr:$src3), RC:$src1),
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(X86andnp (load addr:$src3), RC:$src2))))]>,
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XOP_4V, VEX_W;
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def rmr : IXOPi8Reg<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, VR128:$src3),
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def rmr : IXOPi8Reg<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86memop:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(Int128 VR128:$src1, (bitconvert (loadv2i64 addr:$src2)),
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VR128:$src3))]>,
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[(set RC:$dst, (VT (or (and RC:$src3, RC:$src1),
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(X86andnp RC:$src3, (load addr:$src2)))))]>,
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XOP_4V;
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// For disassembler
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let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
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def rrr_REV : IXOPi8Reg<opc, MRMSrcRegOp4, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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def rrr_REV : IXOPi8Reg<opc, MRMSrcRegOp4, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, XOP_4V, VEX_W;
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// 256-bit Instruction
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def rrrY : IXOPi8Reg<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, VR256:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2, VR256:$src3))]>,
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XOP_4V, VEX_L;
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def rrmY : IXOPi8Reg<opc, MRMSrcMemOp4, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, i256mem:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR256:$dst,
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(Int256 VR256:$src1, VR256:$src2,
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(bitconvert (loadv4i64 addr:$src3))))]>,
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XOP_4V, VEX_W, VEX_L;
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def rmrY : IXOPi8Reg<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, f256mem:$src2, VR256:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR256:$dst,
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(Int256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2)),
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VR256:$src3))]>,
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XOP_4V, VEX_L;
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// For disassembler
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let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
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def rrrY_REV : IXOPi8Reg<opc, MRMSrcRegOp4, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, VR256:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, XOP_4V, VEX_W, VEX_L;
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}
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let ExeDomain = SSEPackedInt in {
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defm VPCMOV : xop4op_int<0xA2, "vpcmov",
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int_x86_xop_vpcmov, int_x86_xop_vpcmov_256>;
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}
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let Predicates = [HasXOP] in {
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def : Pat<(v2i64 (or (and VR128:$src3, VR128:$src1),
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(X86andnp VR128:$src3, VR128:$src2))),
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(VPCMOVrrr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(v4i64 (or (and VR256:$src3, VR256:$src1),
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(X86andnp VR256:$src3, VR256:$src2))),
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(VPCMOVrrrY VR256:$src1, VR256:$src2, VR256:$src3)>;
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defm VPCMOV : xop4op_int<0xA2, "vpcmov", VR128, i128mem, v2i64>;
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defm VPCMOVY : xop4op_int<0xA2, "vpcmov", VR256, i256mem, v4i64>, VEX_L;
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}
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multiclass xop5op<bits<8> opc, string OpcodeStr, SDNode OpNode,
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@ -499,12 +499,22 @@ declare <2 x i64> @llvm.x86.xop.vpcmov(<2 x i64>, <2 x i64>, <2 x i64>) nounwind
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define <4 x i64> @test_mm256_cmov_si256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2) {
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; X32-LABEL: test_mm256_cmov_si256:
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; X32: # BB#0:
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; X32-NEXT: vpcmov %ymm2, %ymm1, %ymm0, %ymm0
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; X32-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
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; X32-NEXT: vinsertf128 $1, %xmm3, %ymm3, %ymm3
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; X32-NEXT: vxorps %ymm3, %ymm2, %ymm3
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; X32-NEXT: vandps %ymm2, %ymm0, %ymm0
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; X32-NEXT: vandps %ymm3, %ymm1, %ymm1
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; X32-NEXT: vorps %ymm1, %ymm0, %ymm0
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; X32-NEXT: retl
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;
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; X64-LABEL: test_mm256_cmov_si256:
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; X64: # BB#0:
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; X64-NEXT: vpcmov %ymm2, %ymm1, %ymm0, %ymm0
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; X64-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
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; X64-NEXT: vinsertf128 $1, %xmm3, %ymm3, %ymm3
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; X64-NEXT: vxorps %ymm3, %ymm2, %ymm3
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; X64-NEXT: vandps %ymm2, %ymm0, %ymm0
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; X64-NEXT: vandps %ymm3, %ymm1, %ymm1
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; X64-NEXT: vorps %ymm1, %ymm0, %ymm0
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; X64-NEXT: retq
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%res = call <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2)
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ret <4 x i64> %res
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@ -725,3 +725,42 @@ define <8 x i16> @test_int_x86_xop_vpcomtruew(<8 x i16> %a0, <8 x i16> %a1) {
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.xop.vpcomtruew(<8 x i16>, <8 x i16>) nounwind readnone
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define <2 x i64> @test_int_x86_xop_vpcmov(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2) {
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; CHECK-LABEL: test_int_x86_xop_vpcmov:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpcmov %xmm2, %xmm1, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%res = call <2 x i64> @llvm.x86.xop.vpcmov(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2) ;
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ret <2 x i64> %res
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}
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declare <2 x i64> @llvm.x86.xop.vpcmov(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone
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define <4 x i64> @test_int_x86_xop_vpcmov_256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2) {
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; CHECK-LABEL: test_int_x86_xop_vpcmov_256:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpcmov %ymm2, %ymm1, %ymm0, %ymm0
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; CHECK-NEXT: retq
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%res = call <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2) ;
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ret <4 x i64> %res
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}
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define <4 x i64> @test_int_x86_xop_vpcmov_256_mr(<4 x i64> %a0, <4 x i64>* %a1, <4 x i64> %a2) {
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; CHECK-LABEL: test_int_x86_xop_vpcmov_256_mr:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpcmov %ymm1, (%rdi), %ymm0, %ymm0
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; CHECK-NEXT: retq
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%vec = load <4 x i64>, <4 x i64>* %a1
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%res = call <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64> %a0, <4 x i64> %vec, <4 x i64> %a2) ;
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ret <4 x i64> %res
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}
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define <4 x i64> @test_int_x86_xop_vpcmov_256_rm(<4 x i64> %a0, <4 x i64> %a1, <4 x i64>* %a2) {
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; CHECK-LABEL: test_int_x86_xop_vpcmov_256_rm:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpcmov (%rdi), %ymm1, %ymm0, %ymm0
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; CHECK-NEXT: retq
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%vec = load <4 x i64>, <4 x i64>* %a2
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%res = call <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %vec) ;
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ret <4 x i64> %res
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}
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declare <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64>, <4 x i64>, <4 x i64>) nounwind readnone
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@ -82,18 +82,23 @@ define <2 x i64> @test_int_x86_xop_vpcmov(<2 x i64> %a0, <2 x i64> %a1, <2 x i64
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; CHECK: # BB#0:
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; CHECK-NEXT: vpcmov %xmm2, %xmm1, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%res = call <2 x i64> @llvm.x86.xop.vpcmov(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2) ;
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ret <2 x i64> %res
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%1 = xor <2 x i64> %a2, <i64 -1, i64 -1>
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%2 = and <2 x i64> %a0, %a2
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%3 = and <2 x i64> %a1, %1
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%4 = or <2 x i64> %2, %3
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ret <2 x i64> %4
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}
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declare <2 x i64> @llvm.x86.xop.vpcmov(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone
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define <4 x i64> @test_int_x86_xop_vpcmov_256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2) {
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; CHECK-LABEL: test_int_x86_xop_vpcmov_256:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpcmov %ymm2, %ymm1, %ymm0, %ymm0
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; CHECK-NEXT: retq
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%res = call <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2) ;
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ret <4 x i64> %res
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%1 = xor <4 x i64> %a2, <i64 -1, i64 -1, i64 -1, i64 -1>
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%2 = and <4 x i64> %a0, %a2
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%3 = and <4 x i64> %a1, %1
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%4 = or <4 x i64> %2, %3
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ret <4 x i64> %4
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}
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define <4 x i64> @test_int_x86_xop_vpcmov_256_mr(<4 x i64> %a0, <4 x i64>* %a1, <4 x i64> %a2) {
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; CHECK-LABEL: test_int_x86_xop_vpcmov_256_mr:
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@ -101,19 +106,24 @@ define <4 x i64> @test_int_x86_xop_vpcmov_256_mr(<4 x i64> %a0, <4 x i64>* %a1,
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; CHECK-NEXT: vpcmov %ymm1, (%rdi), %ymm0, %ymm0
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; CHECK-NEXT: retq
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%vec = load <4 x i64>, <4 x i64>* %a1
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%res = call <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64> %a0, <4 x i64> %vec, <4 x i64> %a2) ;
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ret <4 x i64> %res
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%1 = xor <4 x i64> %a2, <i64 -1, i64 -1, i64 -1, i64 -1>
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%2 = and <4 x i64> %a0, %a2
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%3 = and <4 x i64> %vec, %1
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%4 = or <4 x i64> %2, %3
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ret <4 x i64> %4
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}
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define <4 x i64> @test_int_x86_xop_vpcmov_256_rm(<4 x i64> %a0, <4 x i64> %a1, <4 x i64>* %a2) {
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; CHECK-LABEL: test_int_x86_xop_vpcmov_256_rm:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpcmov (%rdi), %ymm1, %ymm0, %ymm0
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; CHECK-NEXT: retq
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%vec = load <4 x i64>, <4 x i64>* %a2
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%res = call <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %vec) ;
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ret <4 x i64> %res
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%vec = load <4 x i64>, <4 x i64>* %a2
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%1 = xor <4 x i64> %vec, <i64 -1, i64 -1, i64 -1, i64 -1>
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%2 = and <4 x i64> %a0, %vec
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%3 = and <4 x i64> %a1, %1
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%4 = or <4 x i64> %2, %3
|
||||
ret <4 x i64> %4
|
||||
}
|
||||
declare <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64>, <4 x i64>, <4 x i64>) nounwind readnone
|
||||
|
||||
define <4 x i32> @test_int_x86_xop_vphaddbd(<16 x i8> %a0) {
|
||||
; CHECK-LABEL: test_int_x86_xop_vphaddbd:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user