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[ARM] FP16 VSEL codegen
This is a follow up of rL327695 to instruction select more variants of VSELGT and VSELGE, for which it is necessary to custom lower SELECT. More work is required in this area, which will be addressed soon: - more variants need to be regression tested, but this depends on the next point. - first LowerConstantFP need to be adjusted for fp16 values. Differential Revision: https://reviews.llvm.org/D45205 llvm-svn: 329788
This commit is contained in:
Sjoerd Meijer
parent
512991d3bb
commit
10e7e8538f
@ -1047,16 +1047,19 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
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setOperationAction(ISD::SETCC, MVT::i32, Expand);
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setOperationAction(ISD::SETCC, MVT::f16, Expand);
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setOperationAction(ISD::SETCC, MVT::f32, Expand);
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setOperationAction(ISD::SETCC, MVT::f64, Expand);
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setOperationAction(ISD::SELECT, MVT::i32, Custom);
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setOperationAction(ISD::SELECT, MVT::f32, Custom);
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setOperationAction(ISD::SELECT, MVT::f64, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
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if (Subtarget->hasFullFP16()) {
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setOperationAction(ISD::SETCC, MVT::f16, Expand);
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setOperationAction(ISD::SELECT, MVT::f16, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
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}
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// Thumb-1 cannot currently select ARMISD::SUBE.
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if (!Subtarget->isThumb1Only())
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@ -1064,7 +1067,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::BRCOND, MVT::Other, Custom);
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setOperationAction(ISD::BR_CC, MVT::i32, Custom);
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setOperationAction(ISD::BR_CC, MVT::f16, Custom);
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if (Subtarget->hasFullFP16())
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setOperationAction(ISD::BR_CC, MVT::f16, Custom);
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setOperationAction(ISD::BR_CC, MVT::f32, Custom);
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setOperationAction(ISD::BR_CC, MVT::f64, Custom);
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setOperationAction(ISD::BR_JT, MVT::Other, Custom);
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@ -4522,7 +4526,9 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
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// Normalize the fp compare. If RHS is zero we keep it there so we match
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// CMPFPw0 instead of CMPFP.
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if (Subtarget->hasFPARMv8() && !isFloatingPointZero(RHS) &&
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(TrueVal.getValueType() == MVT::f32 || TrueVal.getValueType() == MVT::f64)) {
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(TrueVal.getValueType() == MVT::f16 ||
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TrueVal.getValueType() == MVT::f32 ||
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TrueVal.getValueType() == MVT::f64)) {
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bool swpCmpOps = false;
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bool swpVselOps = false;
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checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
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@ -4,11 +4,11 @@
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; SOFTFP:
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; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+vfp3 | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-VFP3
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; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+vfp4 | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-FP16
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; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+vfp4 | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-FP16,CHECK-SOFTFP-FP16-A32
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; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-FULLFP16
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; RUN: llc < %s -mtriple=thumbv7-none-eabi -mattr=+vfp3 | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-VFP3
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; RUN: llc < %s -mtriple=thumbv7-none-eabi -mattr=+vfp4 | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-FP16
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; RUN: llc < %s -mtriple=thumbv7-none-eabi -mattr=+vfp4 | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-FP16,CHECK-SOFTFP-FP16-T32
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; RUN: llc < %s -mtriple=thumbv7-none-eabi -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-FULLFP16
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; Test fast-isel
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@ -703,37 +703,167 @@ define half @select_cc1() {
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ret half %2
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; CHECK-LABEL: select_cc1:
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; CHECK-HARDFP-FULLFP16: vcmp.f16 s0, s0
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; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-HARDFP-FULLFP16: vseleq.f16 s0, s{{.}}, s{{.}}
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; CHECK-SOFTFP-FP16-A32: vcmp.f32 s0, s0
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; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-SOFTFP-FP16-A32-NEXT: vmoveq.f32 s{{.}}, s{{.}}
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; CHECK-SOFTFP-FP16-T32: vcmp.f32 s0, s0
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; CHECK-SOFTFP-FP16-T32: vmrs APSR_nzcv, fpscr
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; CHECK-SOFTFP-FP16-T32: it eq
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; CHECK-SOFTFP-FP16-T32: vmoveq.f32 s{{.}}, s{{.}}
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}
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; FIXME: more tests need to be added for VSELGE and VSELGT.
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; That is, more combinations of immediate operands that can or can't
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; be encoded as an FP16 immediate need to be added here.
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;
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; 36. VSELGE
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define half @select_cc2() {
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define half @select_cc_ge1() {
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%1 = fcmp nsz oge half undef, 0xH0001
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%2 = select i1 %1, half 0xHC000, half 0xH0002
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ret half %2
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; CHECK-LABEL: select_cc2:
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; CHECK-HARDFP-FULLFP16: vselge.f16 s0, s{{.}}, s{{.}}
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; CHECK-LABEL: select_cc_ge1:
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; CHECK-HARDFP-FULLFP16: vcmpe.f16 s0, s0
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; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-HARDFP-FULLFP16-NEXT: vselge.f16 s0, s{{.}}, s{{.}}
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; CHECK-SOFTFP-FP16-A32: vcmpe.f32 s0, s0
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; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-SOFTFP-FP16-A32-NEXT: vmovge.f32 s{{.}}, s{{.}}
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; CHECK-SOFTFP-FP16-T32: vcmpe.f32 s0, s0
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; CHECK-SOFTFP-FP16-T32-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-SOFTFP-FP16-T32-NEXT: it ge
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; CHECK-SOFTFP-FP16-T32-NEXT: vmovge.f32 s{{.}}, s{{.}}
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}
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;
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; FIXME: add fcmp ole, ult here.
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;
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define half @select_cc_ge3() {
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%1 = fcmp nsz ugt half undef, 0xH0001
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%2 = select i1 %1, half 0xHC000, half 0xH0002
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ret half %2
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; CHECK-LABEL: select_cc_ge3:
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; CHECK-HARDFP-FULLFP16: vcmpe.f16 s0, s0
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; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-HARDFP-FULLFP16-NEXT: vselge.f16 s0, s{{.}}, s{{.}}
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; CHECK-SOFTFP-FP16-A32: vcmpe.f32 s0, s0
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; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-SOFTFP-FP16-A32-NEXT: vmovhi.f32 s{{.}}, s{{.}}
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; CHECK-SOFTFP-FP16-T32: vcmpe.f32 s0, s0
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; CHECK-SOFTFP-FP16-T32-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-SOFTFP-FP16-T32-NEXT: it hi
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; CHECK-SOFTFP-FP16-T32-NEXT: vmovhi.f32 s{{.}}, s{{.}}
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}
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; 37. VSELGT
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define half @select_cc3() {
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define half @select_cc_gt1() {
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%1 = fcmp nsz ogt half undef, 0xH0001
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%2 = select i1 %1, half 0xHC000, half 0xH0002
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ret half %2
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; CHECK-LABEL: select_cc3:
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; CHECK-HARDFP-FULLFP16: vselgt.f16 s0, s{{.}}, s{{.}}
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; CHECK-LABEL: select_cc_gt1:
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; CHECK-HARDFP-FULLFP16: vcmpe.f16 s0, s0
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; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-HARDFP-FULLFP16-NEXT: vselgt.f16 s0, s{{.}}, s{{.}}
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; CHECK-SOFTFP-FP16-A32: vcmpe.f32 s0, s0
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; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-SOFTFP-FP16-A32-NEXT: vmovgt.f32 s{{.}}, s{{.}}
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; CHECK-SOFTFP-FP16-T32: vcmpe.f32 s0, s0
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; CHECK-SOFTFP-FP16-T32-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-SOFTFP-FP16-T32-NEXT: it gt
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; CHECK-SOFTFP-FP16-T32-NEXT: vmovgt.f32 s{{.}}, s{{.}}
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}
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; 38. VSELVS
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define half @select_cc4() {
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%1 = fcmp nsz ueq half undef, 0xH0001
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define half @select_cc_gt2() {
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%1 = fcmp nsz uge half undef, 0xH0001
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%2 = select i1 %1, half 0xHC000, half 0xH0002
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ret half %2
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; CHECK-LABEL: select_cc_gt2:
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; CHECK-HARDFP-FULLFP16: vcmpe.f16 s0, s0
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; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-HARDFP-FULLFP16-NEXT: vselgt.f16 s0, s{{.}}, s{{.}}
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; CHECK-SOFTFP-FP16-A32: vcmpe.f32 s0, s0
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; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-SOFTFP-FP16-A32-NEXT: vmovpl.f32 s{{.}}, s{{.}}
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; CHECK-SOFTFP-FP16-T32: vcmpe.f32 s0, s0
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; CHECK-SOFTFP-FP16-T32-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-SOFTFP-FP16-T32-NEXT: it pl
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; CHECK-SOFTFP-FP16-T32-NEXT: vmovpl.f32 s{{.}}, s{{.}}
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}
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;
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; FIXME: add fcmp ule, olt here.
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;
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; 38. VSELVS
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define float @select_cc4(float %a.coerce) {
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entry:
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%0 = bitcast float %a.coerce to i32
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%tmp.0.extract.trunc = trunc i32 %0 to i16
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%1 = bitcast i16 %tmp.0.extract.trunc to half
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%2 = fcmp nsz ueq half %1, 0xH0001
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%3 = select i1 %2, half 0xHC000, half 0xH0002
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%4 = bitcast half %3 to i16
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%tmp4.0.insert.ext = zext i16 %4 to i32
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%5 = bitcast i32 %tmp4.0.insert.ext to float
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ret float %5
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; CHECK-LABEL: select_cc4:
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; CHECK-HARDFP-FULLFP16: vselvs.f16 s0, s{{.}}, s{{.}}
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; CHECK-HARDFP-FULLFP16: vldr.16 [[S2:s[0-9]]], .LCPI{{.*}}
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; CHECK-HARDFP-FULLFP16: vldr.16 [[S4:s[0-9]]], .LCPI{{.*}}
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; CHECK-HARDFP-FULLFP16: vmov.f16 [[S6:s[0-9]]], #-2.000000e+00
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; CHECK-HARDFP-FULLFP16: vcmp.f16 s0, [[S2]]
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; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-HARDFP-FULLFP16-NEXT: vseleq.f16 [[S0:s[0-9]]], [[S6]], [[S4]]
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; CHECK-HARDFP-FULLFP16-NEXT: vselvs.f16 s0, [[S6]], [[S0]]
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; CHECK-SOFTFP-FP16-A32: vmov [[S6:s[0-9]]], r0
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; CHECK-SOFTFP-FP16-A32: vldr s0, .LCP{{.*}}
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; CHECK-SOFTFP-FP16-A32: vcvtb.f32.f16 [[S6]], [[S6]]
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; CHECK-SOFTFP-FP16-A32: vmov.f32 [[S2:s[0-9]]], #-2.000000e+00
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; CHECK-SOFTFP-FP16-A32: vcmp.f32 [[S6]], s0
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; CHECK-SOFTFP-FP16-A32: vldr [[S4:s[0-9]]], .LCPI{{.*}}
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; CHECK-SOFTFP-FP16-A32: vmrs APSR_nzcv, fpscr
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; CHECK-SOFTFP-FP16-A32: vmoveq.f32 [[S4]], [[S2]]
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; CHECK-SOFTFP-FP16-A32-NEXT: vmovvs.f32 [[S4]], [[S2]]
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; CHECK-SOFTFP-FP16-A32-NEXT: vcvtb.f16.f32 s0, [[S4]]
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; CHECK-SOFTFP-FP16-T32: vmov [[S6:s[0-9]]], r0
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; CHECK-SOFTFP-FP16-T32: vldr s0, .LCP{{.*}}
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; CHECK-SOFTFP-FP16-T32: vcvtb.f32.f16 [[S6]], [[S6]]
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; CHECK-SOFTFP-FP16-T32: vmov.f32 [[S2:s[0-9]]], #-2.000000e+00
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; CHECK-SOFTFP-FP16-T32: vcmp.f32 [[S6]], s0
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; CHECK-SOFTFP-FP16-T32: vldr [[S4:s[0-9]]], .LCPI{{.*}}
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; CHECK-SOFTFP-FP16-T32: vmrs APSR_nzcv, fpscr
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; CHECK-SOFTFP-FP16-T32: it eq
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; CHECK-SOFTFP-FP16-T32: vmoveq.f32 [[S4]], [[S2]]
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; CHECK-SOFTFP-FP16-T32: it vs
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; CHECK-SOFTFP-FP16-T32-NEXT: vmovvs.f32 [[S4]], [[S2]]
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; CHECK-SOFTFP-FP16-T32-NEXT: vcvtb.f16.f32 s0, [[S4]]
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}
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; 39. VSQRT - TODO
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