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PR3739, part 2: Use an explicit store to spill XMM registers. (Previously,

the code tried to use "push", which doesn't exist for XMM registers.)

llvm-svn: 72836
This commit is contained in:
Eli Friedman 2009-06-04 02:32:04 +00:00
parent fd27229206
commit 11070e275f
2 changed files with 29 additions and 4 deletions

View File

@ -2009,16 +2009,24 @@ bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineFunction &MF = *MBB.getParent();
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize);
unsigned CalleeFrameSize = 0;
unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
for (unsigned i = CSI.size(); i != 0; --i) {
unsigned Reg = CSI[i-1].getReg();
const TargetRegisterClass *RegClass = CSI[i-1].getRegClass();
// Add the callee-saved register as live-in. It's killed at the spill.
MBB.addLiveIn(Reg);
if (RegClass != &X86::VR128RegClass) {
CalleeFrameSize += SlotSize;
BuildMI(MBB, MI, DL, get(Opc))
.addReg(Reg, RegState::Kill);
} else {
storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass);
}
}
X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
return true;
}
@ -2036,7 +2044,12 @@ bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
unsigned Reg = CSI[i].getReg();
const TargetRegisterClass *RegClass = CSI[i].getRegClass();
if (RegClass != &X86::VR128RegClass) {
BuildMI(MBB, MI, DL, get(Opc), Reg);
} else {
loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
}
}
return true;
}

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@ -0,0 +1,12 @@
; RUN: llvm-as < %s | llc -o %t1 -f
; RUN: grep "subq.*\\\$40, \\\%rsp" %t1
; RUN: grep "movaps \\\%xmm8, \\\(\\\%rsp\\\)" %t1
; RUN: grep "movaps \\\%xmm7, 16\\\(\\\%rsp\\\)" %t1
target triple = "x86_64-mingw64"
define i32 @a() nounwind {
entry:
tail call void asm sideeffect "", "~{xmm7},~{xmm8},~{dirflag},~{fpsr},~{flags}"() nounwind
ret i32 undef
}