RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 19:23:23 +01:00
Code Issues Projects Releases Wiki Activity

Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.

Browse Source 
llvm-svn: 103459
This commit is contained in:
Evan Cheng 2010-05-11 07:26:32 +00:00
parent 2f2491405a
commit 11130a0a22
5 changed files with 31 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -384,6 +384,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
setOperationAction(ISD::TRAP, MVT::Other, Legal);
// Use the default implementation.
setOperationAction(ISD::VASTART, MVT::Other, Custom);
setOperationAction(ISD::VAARG, MVT::Other, Expand);

4
lib/Target/ARM/ARMInstrInfo.td
View File

@ -791,8 +791,8 @@ def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
}
// A5.4 Permanently UNDEFINED instructions.
def TRAP : AI<(outs), (ins), MiscFrm, NoItinerary, "trap", "",
[/* For disassembly only; pattern left blank */]>,
let isBarrier = 1, isTerminator = 1 in
def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, "trap", [(trap)]>,
Requires<[IsARM]> {
let Inst{27-25} = 0b011;
let Inst{24-20} = 0b11111;

5
lib/Target/ARM/ARMInstrThumb.td
View File

@ -417,9 +417,10 @@ def tSVC : T1pI<(outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc", []>,
}
}
// A8.6.16 B: Encoding T1 -- for disassembly only
// A8.6.16 B: Encoding T1
// If Inst{11-8} == 0b1110 then UNDEFINED
def tTRAP : T1I<(outs), (ins), IIC_Br, "trap", []>, Encoding16 {
let isBarrier = 1, isTerminator = 1 in
def tTRAP : TI<(outs), (ins), IIC_Br, "trap", [(trap)]>, Encoding16 {
let Inst{15-12} = 0b1101;
let Inst{11-8} = 0b1110;
}

12
test/CodeGen/ARM/trap.ll Normal file
View File

@ -0,0 +1,12 @@
; RUN: llc < %s -march=arm | FileCheck %s
; rdar://7961298
define arm_apcscc void @t() nounwind {
entry:
; CHECK: t:
; CHECK: trap
call void @llvm.trap()
unreachable
}
declare void @llvm.trap() nounwind

12
test/CodeGen/Thumb/trap.ll Normal file
View File

@ -0,0 +1,12 @@
; RUN: llc < %s -march=thumb | FileCheck %s
; rdar://7961298
define arm_apcscc void @t() nounwind {
entry:
; CHECK: t:
; CHECK: trap
call void @llvm.trap()
unreachable
}
declare void @llvm.trap() nounwind