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R600: Better fix for bug 20982
Just do the left shift as unsigned to avoid the UB. llvm-svn: 218092
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@ -1896,7 +1896,8 @@ template <typename IntTy>
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static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
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uint32_t Offset, uint32_t Width) {
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if (Width + Offset < 32) {
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IntTy Result = (Src0 << (32 - Offset - Width)) >> (32 - Width);
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uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
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IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
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return DAG.getConstant(Result, MVT::i32);
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}
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@ -2053,12 +2054,8 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
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// Avoid undefined left shift of a negative in the constant fold.
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// TODO: I'm not sure what the behavior of the hardware is, this should
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// probably follow that instead.
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int32_t Val = CVal->getSExtValue();
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if (Val < 0)
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return SDValue();
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return constantFoldBFE<int32_t>(DAG,
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Val,
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CVal->getSExtValue(),
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OffsetVal,
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WidthVal);
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}
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@ -370,13 +370,12 @@ define void @bfe_i32_constant_fold_test_15(i32 addrspace(1)* %out) nounwind {
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ret void
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}
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; FIXME: This should fold to something
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; FUNC-LABEL: @bfe_i32_constant_fold_test_16
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; SI: S_BFE_I32 [[SREG:s[0-9]+]], -1, 0x70001
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; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], [[SREG]]
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; SI-NOT: BFE
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; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], -1
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; SI: BUFFER_STORE_DWORD [[VREG]],
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; SI: S_ENDPGM
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; EG-NOT: BFE
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define void @bfe_i32_constant_fold_test_16(i32 addrspace(1)* %out) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 4294967295, i32 1, i32 7) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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