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[PowerPC][Power10] Fix VINS* (vector insert byte/half/word) instructions to have i32 arguments.
Previously, the vins* intrinsic was incorrectly defined to have its second and third argument arguments as an i64. This patch fixes the second and third argument of the vins* instruction and intrinsic to have i32s instead. Differential Revision: https://reviews.llvm.org/D83497
This commit is contained in:
Amy Kwan
parent
be5802be10
commit
1157465de4
@ -468,27 +468,27 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
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// P10 Vector Insert.
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def int_ppc_altivec_vinsblx : GCCBuiltin<"__builtin_altivec_vinsblx">,
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Intrinsic<[llvm_v16i8_ty],
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[llvm_v16i8_ty, llvm_i64_ty, llvm_i64_ty],
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[llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vinsbrx : GCCBuiltin<"__builtin_altivec_vinsbrx">,
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Intrinsic<[llvm_v16i8_ty],
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[llvm_v16i8_ty, llvm_i64_ty, llvm_i64_ty],
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[llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vinshlx : GCCBuiltin<"__builtin_altivec_vinshlx">,
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Intrinsic<[llvm_v8i16_ty],
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[llvm_v8i16_ty, llvm_i64_ty, llvm_i64_ty],
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[llvm_v8i16_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vinshrx : GCCBuiltin<"__builtin_altivec_vinshrx">,
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Intrinsic<[llvm_v8i16_ty],
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[llvm_v8i16_ty, llvm_i64_ty, llvm_i64_ty],
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[llvm_v8i16_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vinswlx : GCCBuiltin<"__builtin_altivec_vinswlx">,
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v4i32_ty, llvm_i64_ty, llvm_i64_ty],
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[llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vinswrx : GCCBuiltin<"__builtin_altivec_vinswrx">,
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v4i32_ty, llvm_i64_ty, llvm_i64_ty],
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[llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vinsdlx : GCCBuiltin<"__builtin_altivec_vinsdlx">,
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Intrinsic<[llvm_v2i64_ty],
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@ -525,7 +525,7 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
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// P10 Vector Insert with immediate.
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def int_ppc_altivec_vinsw :
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v4i32_ty, llvm_i64_ty, llvm_i32_ty],
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[llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem, ImmArg<ArgIndex<2>>]>;
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def int_ppc_altivec_vinsd :
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Intrinsic<[llvm_v2i64_ty],
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@ -242,15 +242,6 @@ class VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
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}
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// VX-Form: [PO VRT / UIM RB XO].
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// We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent
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// "/ UIM" (unused bit followed by a 4-bit immediate)
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// Destructive (insert) forms are suffixed with _ins.
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class VXForm_VRT5_UIM5_RB5_ins<bits<11> xo, string opc, list<dag> pattern>
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: VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, g8rc:$rB),
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!strconcat(opc, " $vD, $rB, $UIM"), IIC_VecGeneral, pattern>,
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RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
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// VX-Form: [PO VRT RA VRB XO].
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// Destructive (insert) forms are suffixed with _ins.
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class VXForm_VTB5_RA5_ins<bits<11> xo, string opc, list<dag> pattern>
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@ -261,7 +252,7 @@ class VXForm_VTB5_RA5_ins<bits<11> xo, string opc, list<dag> pattern>
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// VX-Form: [PO VRT RA RB XO].
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// Destructive (insert) forms are suffixed with _ins.
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class VXForm_VRT5_RAB5_ins<bits<11> xo, string opc, list<dag> pattern>
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: VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB),
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: VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, gprc:$rA, gprc:$rB),
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!strconcat(opc, " $vD, $rA, $rB"), IIC_VecGeneral, pattern>,
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RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
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@ -813,16 +804,18 @@ let Predicates = [IsISA3_1] in {
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(int_ppc_altivec_vsrdbi v16i8:$VRA,
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v16i8:$VRB,
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i32:$SH))]>;
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def VINSW :
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VXForm_VRT5_UIM5_RB5_ins<207, "vinsw",
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[(set v4i32:$vD,
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(int_ppc_altivec_vinsw v4i32:$vDi, i64:$rB,
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timm:$UIM))]>;
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def VINSW :
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VXForm_1<207, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, gprc:$rB),
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"vinsw $vD, $rB, $UIM", IIC_VecGeneral,
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[(set v4i32:$vD,
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(int_ppc_altivec_vinsw v4i32:$vDi, i32:$rB, timm:$UIM))]>,
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RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
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def VINSD :
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VXForm_VRT5_UIM5_RB5_ins<463, "vinsd",
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[(set v2i64:$vD,
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(int_ppc_altivec_vinsd v2i64:$vDi, i64:$rB,
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timm:$UIM))]>;
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VXForm_1<463, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, g8rc:$rB),
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"vinsd $vD, $rB, $UIM", IIC_VecGeneral,
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[(set v2i64:$vD,
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(int_ppc_altivec_vinsd v2i64:$vDi, i64:$rB, timm:$UIM))]>,
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RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
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def VINSBVLX :
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VXForm_VTB5_RA5_ins<15, "vinsbvlx",
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[(set v16i8:$vD,
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@ -856,44 +849,45 @@ let Predicates = [IsISA3_1] in {
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def VINSBLX :
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VXForm_VRT5_RAB5_ins<527, "vinsblx",
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[(set v16i8:$vD,
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(int_ppc_altivec_vinsblx v16i8:$vDi, i64:$rA,
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i64:$rB))]>;
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(int_ppc_altivec_vinsblx v16i8:$vDi, i32:$rA,
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i32:$rB))]>;
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def VINSBRX :
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VXForm_VRT5_RAB5_ins<783, "vinsbrx",
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[(set v16i8:$vD,
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(int_ppc_altivec_vinsbrx v16i8:$vDi, i64:$rA,
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i64:$rB))]>;
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(int_ppc_altivec_vinsbrx v16i8:$vDi, i32:$rA,
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i32:$rB))]>;
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def VINSHLX :
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VXForm_VRT5_RAB5_ins<591, "vinshlx",
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[(set v8i16:$vD,
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(int_ppc_altivec_vinshlx v8i16:$vDi, i64:$rA,
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i64:$rB))]>;
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(int_ppc_altivec_vinshlx v8i16:$vDi, i32:$rA,
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i32:$rB))]>;
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def VINSHRX :
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VXForm_VRT5_RAB5_ins<847, "vinshrx",
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[(set v8i16:$vD,
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(int_ppc_altivec_vinshrx v8i16:$vDi, i64:$rA,
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i64:$rB))]>;
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(int_ppc_altivec_vinshrx v8i16:$vDi, i32:$rA,
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i32:$rB))]>;
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def VINSWLX :
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VXForm_VRT5_RAB5_ins<655, "vinswlx",
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[(set v4i32:$vD,
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(int_ppc_altivec_vinswlx v4i32:$vDi, i64:$rA,
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i64:$rB))]>;
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(int_ppc_altivec_vinswlx v4i32:$vDi, i32:$rA,
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i32:$rB))]>;
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def VINSWRX :
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VXForm_VRT5_RAB5_ins<911, "vinswrx",
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[(set v4i32:$vD,
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(int_ppc_altivec_vinswrx v4i32:$vDi, i64:$rA,
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i64:$rB))]>;
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(int_ppc_altivec_vinswrx v4i32:$vDi, i32:$rA,
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i32:$rB))]>;
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def VINSDLX :
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VXForm_VRT5_RAB5_ins<719, "vinsdlx",
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[(set v2i64:$vD,
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(int_ppc_altivec_vinsdlx v2i64:$vDi, i64:$rA,
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i64:$rB))]>;
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VXForm_1<719, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB),
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"vinsdlx $vD, $rA, $rB", IIC_VecGeneral,
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[(set v2i64:$vD,
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(int_ppc_altivec_vinsdlx v2i64:$vDi, i64:$rA, i64:$rB))]>,
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RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
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def VINSDRX :
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VXForm_VRT5_RAB5_ins<975, "vinsdrx",
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[(set v2i64:$vD,
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(int_ppc_altivec_vinsdrx v2i64:$vDi, i64:$rA,
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i64:$rB))]>;
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VXForm_1<975, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB),
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"vinsdrx $vD, $rA, $rB", IIC_VecGeneral,
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[(set v2i64:$vD,
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(int_ppc_altivec_vinsdrx v2i64:$vDi, i64:$rA, i64:$rB))]>,
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RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
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def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vpdepd $vD, $vA, $vB", IIC_VecGeneral,
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[(set v2i64:$vD,
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@ -82,71 +82,71 @@ entry:
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}
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declare <2 x i64> @llvm.ppc.vsx.xxblendvd(<2 x i64>, <2 x i64>, <2 x i64>)
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define <16 x i8> @testVINSBLX(<16 x i8> %a, i64 %b, i64 %c) {
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define <16 x i8> @testVINSBLX(<16 x i8> %a, i32 %b, i32 %c) {
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; CHECK-LABEL: testVINSBLX:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vinsblx v2, r5, r6
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <16 x i8> @llvm.ppc.altivec.vinsblx(<16 x i8> %a, i64 %b, i64 %c)
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%0 = tail call <16 x i8> @llvm.ppc.altivec.vinsblx(<16 x i8> %a, i32 %b, i32 %c)
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ret <16 x i8> %0
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}
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declare <16 x i8> @llvm.ppc.altivec.vinsblx(<16 x i8>, i64, i64)
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declare <16 x i8> @llvm.ppc.altivec.vinsblx(<16 x i8>, i32, i32)
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define <16 x i8> @testVINSBRX(<16 x i8> %a, i64 %b, i64 %c) {
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define <16 x i8> @testVINSBRX(<16 x i8> %a, i32 %b, i32 %c) {
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; CHECK-LABEL: testVINSBRX:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vinsbrx v2, r5, r6
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbrx(<16 x i8> %a, i64 %b, i64 %c)
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%0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbrx(<16 x i8> %a, i32 %b, i32 %c)
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ret <16 x i8> %0
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}
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declare <16 x i8> @llvm.ppc.altivec.vinsbrx(<16 x i8>, i64, i64)
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declare <16 x i8> @llvm.ppc.altivec.vinsbrx(<16 x i8>, i32, i32)
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define <8 x i16> @testVINSHLX(<8 x i16> %a, i64 %b, i64 %c) {
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define <8 x i16> @testVINSHLX(<8 x i16> %a, i32 %b, i32 %c) {
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; CHECK-LABEL: testVINSHLX:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vinshlx v2, r5, r6
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <8 x i16> @llvm.ppc.altivec.vinshlx(<8 x i16> %a, i64 %b, i64 %c)
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%0 = tail call <8 x i16> @llvm.ppc.altivec.vinshlx(<8 x i16> %a, i32 %b, i32 %c)
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ret <8 x i16> %0
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}
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declare <8 x i16> @llvm.ppc.altivec.vinshlx(<8 x i16>, i64, i64)
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declare <8 x i16> @llvm.ppc.altivec.vinshlx(<8 x i16>, i32, i32)
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define <8 x i16> @testVINSHRX(<8 x i16> %a, i64 %b, i64 %c) {
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define <8 x i16> @testVINSHRX(<8 x i16> %a, i32 %b, i32 %c) {
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; CHECK-LABEL: testVINSHRX:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vinshrx v2, r5, r6
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <8 x i16> @llvm.ppc.altivec.vinshrx(<8 x i16> %a, i64 %b, i64 %c)
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%0 = tail call <8 x i16> @llvm.ppc.altivec.vinshrx(<8 x i16> %a, i32 %b, i32 %c)
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ret <8 x i16> %0
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}
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declare <8 x i16> @llvm.ppc.altivec.vinshrx(<8 x i16>, i64, i64)
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declare <8 x i16> @llvm.ppc.altivec.vinshrx(<8 x i16>, i32, i32)
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define <4 x i32> @testVINSWLX(<4 x i32> %a, i64 %b, i64 %c) {
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define <4 x i32> @testVINSWLX(<4 x i32> %a, i32 %b, i32 %c) {
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; CHECK-LABEL: testVINSWLX:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vinswlx v2, r5, r6
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <4 x i32> @llvm.ppc.altivec.vinswlx(<4 x i32> %a, i64 %b, i64 %c)
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%0 = tail call <4 x i32> @llvm.ppc.altivec.vinswlx(<4 x i32> %a, i32 %b, i32 %c)
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ret <4 x i32> %0
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}
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declare <4 x i32> @llvm.ppc.altivec.vinswlx(<4 x i32>, i64, i64)
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declare <4 x i32> @llvm.ppc.altivec.vinswlx(<4 x i32>, i32, i32)
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define <4 x i32> @testVINSWRX(<4 x i32> %a, i64 %b, i64 %c) {
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define <4 x i32> @testVINSWRX(<4 x i32> %a, i32 %b, i32 %c) {
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; CHECK-LABEL: testVINSWRX:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vinswrx v2, r5, r6
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <4 x i32> @llvm.ppc.altivec.vinswrx(<4 x i32> %a, i64 %b, i64 %c)
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%0 = tail call <4 x i32> @llvm.ppc.altivec.vinswrx(<4 x i32> %a, i32 %b, i32 %c)
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ret <4 x i32> %0
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}
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declare <4 x i32> @llvm.ppc.altivec.vinswrx(<4 x i32>, i64, i64)
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declare <4 x i32> @llvm.ppc.altivec.vinswrx(<4 x i32>, i32, i32)
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define <2 x i64> @testVINSDLX(<2 x i64> %a, i64 %b, i64 %c) {
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; CHECK-LABEL: testVINSDLX:
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@ -232,16 +232,16 @@ entry:
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}
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declare <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32>, i64, <4 x i32>)
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define <4 x i32> @testVINSW(<4 x i32> %a, i64 %b) {
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define <4 x i32> @testVINSW(<4 x i32> %a, i32 %b) {
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; CHECK-LABEL: testVINSW:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vinsw v2, r5, 1
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> %a, i64 %b, i32 1)
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%0 = tail call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> %a, i32 %b, i32 1)
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ret <4 x i32> %0
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}
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declare <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32>, i64, i32 immarg)
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declare <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32>, i32, i32 immarg)
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define <2 x i64> @testVINSD(<2 x i64> %a, i64 %b) {
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; CHECK-LABEL: testVINSD:
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