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https://github.com/RPCS3/llvm-mirror.git
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Fix a crash compiling 254.gap for Thumb2. The Thumb2 add/sub with 12-bit
immediate instructions cannot set the condition codes, so they do not have the extra cc_out operand. We hit an assertion during tail duplication because the instruction being duplicated had more operands that expected. llvm-svn: 98001
This commit is contained in:
Bob Wilson
parent
db47eab2a3
commit
116599fe52
@ -331,9 +331,9 @@ multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
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let Inst{15} = 0;
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}
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// 12-bit imm
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def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
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!strconcat(opc, "w"), "\t$dst, $lhs, $rhs",
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[(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> {
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def ri12 : T2I<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
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!strconcat(opc, "w"), "\t$dst, $lhs, $rhs",
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[(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> {
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let Inst{31-27} = 0b11110;
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let Inst{25} = 1;
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let Inst{24} = 0;
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@ -164,6 +164,7 @@ void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
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continue;
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}
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bool HasCCOut = true;
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if (BaseReg == ARM::SP) {
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// sub sp, sp, #imm7
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if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
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@ -195,6 +196,7 @@ void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
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NumBytes = 0;
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} else if (ThisVal < 4096) {
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Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
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HasCCOut = false;
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NumBytes = 0;
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} else {
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// FIXME: Move this to ARMAddressingModes.h?
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@ -207,9 +209,12 @@ void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
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}
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// Build the new ADD / SUB.
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AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
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.addReg(BaseReg, RegState::Kill)
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.addImm(ThisVal)));
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MachineInstrBuilder MIB =
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AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
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.addReg(BaseReg, RegState::Kill)
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.addImm(ThisVal));
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if (HasCCOut)
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AddDefaultCC(MIB);
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BaseReg = DestReg;
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}
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@ -328,7 +333,6 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
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if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
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Offset += MI.getOperand(FrameRegIdx+1).getImm();
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bool isSP = FrameReg == ARM::SP;
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unsigned PredReg;
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if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
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// Turn it into a move.
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@ -342,6 +346,9 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
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return true;
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}
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bool isSP = FrameReg == ARM::SP;
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bool HasCCOut = Opcode != ARM::t2ADDri12;
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if (Offset < 0) {
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Offset = -Offset;
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isSub = true;
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@ -354,17 +361,24 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
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if (ARM_AM::getT2SOImmVal(Offset) != -1) {
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MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
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MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
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// Add cc_out operand if the original instruction did not have one.
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if (!HasCCOut)
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MI.addOperand(MachineOperand::CreateReg(0, false));
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Offset = 0;
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return true;
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}
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// Another common case: imm12.
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if (Offset < 4096) {
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if (Offset < 4096 &&
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(!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
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unsigned NewOpc = isSP
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? (isSub ? ARM::t2SUBrSPi12 : ARM::t2ADDrSPi12)
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: (isSub ? ARM::t2SUBri12 : ARM::t2ADDri12);
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MI.setDesc(TII.get(NewOpc));
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MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
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MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
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// Remove the cc_out operand.
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if (HasCCOut)
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MI.RemoveOperand(MI.getNumOperands()-1);
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Offset = 0;
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return true;
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}
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@ -380,6 +394,10 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
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assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
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"Bit extraction didn't work?");
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MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
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// Add cc_out operand if the original instruction did not have one.
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if (!HasCCOut)
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MI.addOperand(MachineOperand::CreateReg(0, false));
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} else {
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// AddrMode4 and AddrMode6 cannot handle any offset.
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266
test/CodeGen/Thumb2/2010-03-08-addi12-ccout.ll
Normal file
266
test/CodeGen/Thumb2/2010-03-08-addi12-ccout.ll
Normal file
@ -0,0 +1,266 @@
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin
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@.str41196 = external constant [2 x i8], align 4 ; <[2 x i8]*> [#uses=1]
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declare arm_apcscc void @syStopraw(i32) nounwind
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declare arm_apcscc i32 @SyFopen(i8*, i8*) nounwind
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declare arm_apcscc i8* @SyFgets(i8*, i32) nounwind
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define arm_apcscc void @SyHelp(i8* nocapture %topic, i32 %fin) nounwind {
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entry:
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%line = alloca [256 x i8], align 4 ; <[256 x i8]*> [#uses=1]
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%secname = alloca [1024 x i8], align 4 ; <[1024 x i8]*> [#uses=0]
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%last = alloca [256 x i8], align 4 ; <[256 x i8]*> [#uses=1]
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%last2 = alloca [256 x i8], align 4 ; <[256 x i8]*> [#uses=1]
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br i1 undef, label %bb, label %bb2
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bb: ; preds = %entry
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br i1 undef, label %bb2, label %bb3
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bb2: ; preds = %bb, %entry
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br label %bb3
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bb3: ; preds = %bb2, %bb
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%storemerge = phi i32 [ 0, %bb2 ], [ 1, %bb ] ; <i32> [#uses=1]
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br i1 undef, label %bb19, label %bb20
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bb19: ; preds = %bb3
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br label %bb20
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bb20: ; preds = %bb19, %bb3
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br i1 undef, label %bb25, label %bb26
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bb25: ; preds = %bb20
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br label %bb26
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bb26: ; preds = %bb25, %bb20
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%offset.2 = phi i32 [ -2, %bb25 ], [ 0, %bb20 ] ; <i32> [#uses=1]
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br i1 undef, label %bb.nph508, label %bb49
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bb.nph508: ; preds = %bb26
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unreachable
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bb49: ; preds = %bb26
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br i1 undef, label %bb51, label %bb50
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bb50: ; preds = %bb49
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br i1 undef, label %bb51, label %bb104
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bb51: ; preds = %bb50, %bb49
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unreachable
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bb104: ; preds = %bb50
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br i1 undef, label %bb106, label %bb105
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bb105: ; preds = %bb104
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br i1 undef, label %bb106, label %bb161
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bb106: ; preds = %bb105, %bb104
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unreachable
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bb161: ; preds = %bb105
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br i1 false, label %bb163, label %bb162
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bb162: ; preds = %bb161
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br i1 undef, label %bb163, label %bb224
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bb163: ; preds = %bb162, %bb161
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unreachable
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bb224: ; preds = %bb162
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%0 = call arm_apcscc i32 @SyFopen(i8* undef, i8* getelementptr inbounds ([2 x i8]* @.str41196, i32 0, i32 0)) nounwind ; <i32> [#uses=2]
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br i1 false, label %bb297, label %bb300
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bb297: ; preds = %bb224
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unreachable
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bb300: ; preds = %bb224
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%1 = icmp eq i32 %offset.2, -1 ; <i1> [#uses=1]
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br label %bb440
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bb307: ; preds = %isdigit1498.exit67
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br label %bb308
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bb308: ; preds = %bb440, %bb307
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br i1 undef, label %bb309, label %isdigit1498.exit67
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isdigit1498.exit67: ; preds = %bb308
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br i1 undef, label %bb309, label %bb307
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bb309: ; preds = %isdigit1498.exit67, %bb308
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br i1 undef, label %bb310, label %bb313
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bb310: ; preds = %bb309
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br label %bb313
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bb313: ; preds = %bb310, %bb309
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br i1 false, label %bb318, label %bb317
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bb317: ; preds = %bb313
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%2 = icmp sgt i8 undef, -1 ; <i1> [#uses=1]
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br i1 %2, label %bb.i.i73, label %bb1.i.i74
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bb.i.i73: ; preds = %bb317
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br i1 false, label %bb318, label %bb329.outer
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bb1.i.i74: ; preds = %bb317
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unreachable
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bb318: ; preds = %bb.i.i73, %bb313
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ret void
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bb329.outer: ; preds = %bb.i.i73
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br i1 undef, label %bb333, label %bb329.us.us
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bb329.us.us: ; preds = %bb329.us.us, %bb329.outer
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br i1 undef, label %bb333, label %bb329.us.us
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bb333: ; preds = %bb329.us.us, %bb329.outer
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%match.0.lcssa = phi i32 [ undef, %bb329.us.us ], [ 2, %bb329.outer ] ; <i32> [#uses=2]
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br i1 undef, label %bb335, label %bb388
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bb335: ; preds = %bb333
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%3 = and i1 undef, %1 ; <i1> [#uses=1]
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br i1 %3, label %bb339, label %bb348
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bb339: ; preds = %bb335
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br i1 false, label %bb340, label %bb345
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bb340: ; preds = %bb339
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br i1 undef, label %return, label %bb341
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bb341: ; preds = %bb340
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ret void
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bb345: ; preds = %bb345, %bb339
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%4 = phi i8 [ %5, %bb345 ], [ undef, %bb339 ] ; <i8> [#uses=0]
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%indvar670 = phi i32 [ %tmp673, %bb345 ], [ 0, %bb339 ] ; <i32> [#uses=1]
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%tmp673 = add i32 %indvar670, 1 ; <i32> [#uses=2]
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%scevgep674 = getelementptr [256 x i8]* %last, i32 0, i32 %tmp673 ; <i8*> [#uses=1]
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%5 = load i8* %scevgep674, align 1 ; <i8> [#uses=1]
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br i1 undef, label %bb347, label %bb345
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bb347: ; preds = %bb345
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br label %bb348
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bb348: ; preds = %bb347, %bb335
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br i1 false, label %bb352, label %bb356
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bb352: ; preds = %bb348
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unreachable
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bb356: ; preds = %bb348
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br i1 undef, label %bb360, label %bb369
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bb360: ; preds = %bb356
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br i1 false, label %bb361, label %bb366
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bb361: ; preds = %bb360
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br i1 undef, label %return, label %bb362
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bb362: ; preds = %bb361
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ret void
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bb366: ; preds = %bb366, %bb360
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%indvar662 = phi i32 [ %tmp665, %bb366 ], [ 0, %bb360 ] ; <i32> [#uses=1]
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%tmp665 = add i32 %indvar662, 1 ; <i32> [#uses=2]
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%scevgep666 = getelementptr [256 x i8]* %last2, i32 0, i32 %tmp665 ; <i8*> [#uses=1]
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%6 = load i8* %scevgep666, align 1 ; <i8> [#uses=0]
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br i1 false, label %bb368, label %bb366
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bb368: ; preds = %bb366
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br label %bb369
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bb369: ; preds = %bb368, %bb356
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br i1 undef, label %bb373, label %bb388
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bb373: ; preds = %bb383, %bb369
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%7 = call arm_apcscc i8* @SyFgets(i8* undef, i32 %0) nounwind ; <i8*> [#uses=1]
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%8 = icmp eq i8* %7, null ; <i1> [#uses=1]
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br i1 %8, label %bb375, label %bb383
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bb375: ; preds = %bb373
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%9 = icmp eq i32 %storemerge, 0 ; <i1> [#uses=1]
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br i1 %9, label %return, label %bb376
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bb376: ; preds = %bb375
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ret void
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bb383: ; preds = %bb373
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%10 = load i8* undef, align 1 ; <i8> [#uses=1]
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%cond1 = icmp eq i8 %10, 46 ; <i1> [#uses=1]
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br i1 %cond1, label %bb373, label %bb388
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bb388: ; preds = %bb383, %bb369, %bb333
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%match.1140 = phi i32 [ %match.0.lcssa, %bb369 ], [ 0, %bb333 ], [ %match.0.lcssa, %bb383 ] ; <i32> [#uses=1]
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br label %bb391
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bb390: ; preds = %isdigit1498.exit83, %bb392
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%indvar.next725 = add i32 %indvar724, 1 ; <i32> [#uses=1]
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br label %bb391
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bb391: ; preds = %bb390, %bb388
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%indvar724 = phi i32 [ %indvar.next725, %bb390 ], [ 0, %bb388 ] ; <i32> [#uses=2]
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%11 = load i8* undef, align 1 ; <i8> [#uses=0]
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br i1 false, label %bb395, label %bb392
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bb392: ; preds = %bb391
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br i1 undef, label %bb390, label %isdigit1498.exit83
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isdigit1498.exit83: ; preds = %bb392
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br i1 undef, label %bb390, label %bb395
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bb394: ; preds = %isdigit1498.exit87
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br label %bb395
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bb395: ; preds = %bb394, %isdigit1498.exit83, %bb391
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%storemerge14.sum = add i32 %indvar724, undef ; <i32> [#uses=1]
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%p.26 = getelementptr [256 x i8]* %line, i32 0, i32 %storemerge14.sum ; <i8*> [#uses=1]
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br i1 undef, label %bb400, label %isdigit1498.exit87
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isdigit1498.exit87: ; preds = %bb395
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br i1 false, label %bb400, label %bb394
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bb400: ; preds = %isdigit1498.exit87, %bb395
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br i1 undef, label %bb402, label %bb403
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bb402: ; preds = %bb400
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%12 = getelementptr inbounds i8* %p.26, i32 undef ; <i8*> [#uses=1]
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br label %bb403
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bb403: ; preds = %bb402, %bb400
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%p.29 = phi i8* [ %12, %bb402 ], [ undef, %bb400 ] ; <i8*> [#uses=0]
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br i1 undef, label %bb405, label %bb404
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bb404: ; preds = %bb403
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br i1 undef, label %bb405, label %bb407
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bb405: ; preds = %bb404, %bb403
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br i1 undef, label %return, label %bb406
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bb406: ; preds = %bb405
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call arm_apcscc void @syStopraw(i32 %fin) nounwind
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ret void
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bb407: ; preds = %bb404
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%cond = icmp eq i32 %match.1140, 2 ; <i1> [#uses=1]
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br i1 %cond, label %bb408, label %bb428
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bb408: ; preds = %bb407
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unreachable
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bb428: ; preds = %bb407
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br label %bb440
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bb440: ; preds = %bb428, %bb300
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%13 = call arm_apcscc i8* @SyFgets(i8* undef, i32 %0) nounwind ; <i8*> [#uses=0]
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br i1 false, label %bb442, label %bb308
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bb442: ; preds = %bb440
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unreachable
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return: ; preds = %bb405, %bb375, %bb361, %bb340
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ret void
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}
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