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GlobalISel: Add type argument to getRegBankFromRegClass

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AMDGPU can't unambiguously go back from the selected instruction
register class to the register bank without knowing if this was used
in a boolean context.
This commit is contained in:
Matt Arsenault 2019-11-08 21:21:00 -08:00 committed by Matt Arsenault
parent b8b1c0544c
commit 116c5991ec
13 changed files with 43 additions and 30 deletions
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3
include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
View File

@ -574,7 +574,8 @@ bool InstructionSelector::executeMatchTable(
assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
if (!MO.isReg() ||
&RBI.getRegBankFromRegClass(*TRI.getRegClass(RCEnum)) !=
&RBI.getRegBankFromRegClass(*TRI.getRegClass(RCEnum),
MRI.getType(MO.getReg())) !=
RBI.getRegBank(MO.getReg(), MRI, TRI)) {
if (handleReject() == RejectAndGiveUp)
return false;

5
include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
View File

@ -20,6 +20,7 @@
#include "llvm/ADT/iterator_range.h"
#include "llvm/CodeGen/Register.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/LowLevelTypeImpl.h"
#include <cassert>
#include <initializer_list>
#include <memory>
@ -543,7 +544,7 @@ public:
const RegisterBank *
getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx,
const TargetInstrInfo &TII,
const TargetRegisterInfo &TRI) const;
const MachineRegisterInfo &MRI) const;
/// Helper method to apply something that is like the default mapping.
/// Basically, that means that \p OpdMapper.getMI() is left untouched
@ -599,7 +600,7 @@ public:
///
/// \todo This should be TableGen'ed.
virtual const RegisterBank &
getRegBankFromRegClass(const TargetRegisterClass &RC) const {
getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const {
llvm_unreachable("The target must override this method");
}

20
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
View File

@ -82,15 +82,18 @@ bool RegisterBankInfo::verify(const TargetRegisterInfo &TRI) const {
const RegisterBank *
RegisterBankInfo::getRegBank(Register Reg, const MachineRegisterInfo &MRI,
const TargetRegisterInfo &TRI) const {
if (Register::isPhysicalRegister(Reg))
return &getRegBankFromRegClass(getMinimalPhysRegClass(Reg, TRI));
if (Register::isPhysicalRegister(Reg)) {
// FIXME: This was probably a copy to a virtual register that does have a
// type we could use.
return &getRegBankFromRegClass(getMinimalPhysRegClass(Reg, TRI), LLT());
}
assert(Reg && "NoRegister does not have a register bank");
const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>())
return RB;
if (auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())
return &getRegBankFromRegClass(*RC);
return &getRegBankFromRegClass(*RC, MRI.getType(Reg));
return nullptr;
}
@ -108,15 +111,18 @@ RegisterBankInfo::getMinimalPhysRegClass(Register Reg,
const RegisterBank *RegisterBankInfo::getRegBankFromConstraints(
const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII,
const TargetRegisterInfo &TRI) const {
const MachineRegisterInfo &MRI) const {
const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
// The mapping of the registers may be available via the
// register class constraints.
const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, &TRI);
const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, TRI);
if (!RC)
return nullptr;
const RegisterBank &RegBank = getRegBankFromRegClass(*RC);
Register Reg = MI.getOperand(OpIdx).getReg();
const RegisterBank &RegBank = getRegBankFromRegClass(*RC, MRI.getType(Reg));
// Sanity check that the target properly implemented getRegBankFromRegClass.
assert(RegBank.covers(*RC) &&
"The mapping of the register bank does not make sense");
@ -195,7 +201,7 @@ RegisterBankInfo::getInstrMappingImpl(const MachineInstr &MI) const {
if (!CurRegBank) {
// If this is a target specific instruction, we can deduce
// the register bank from the encoding constraints.
CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, TRI);
CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, MRI);
if (!CurRegBank) {
// All our attempts failed, give up.
CompleteMapping = false;

5
lib/Target/AArch64/AArch64RegisterBankInfo.cpp
View File

@ -222,8 +222,9 @@ unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A,
return RegisterBankInfo::copyCost(A, B, Size);
}
const RegisterBank &AArch64RegisterBankInfo::getRegBankFromRegClass(
const TargetRegisterClass &RC) const {
const RegisterBank &
AArch64RegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
LLT) const {
switch (RC.getID()) {
case AArch64::FPR8RegClassID:
case AArch64::FPR16RegClassID:

4
lib/Target/AArch64/AArch64RegisterBankInfo.h
View File

@ -132,8 +132,8 @@ public:
unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
unsigned Size) const override;
const RegisterBank &
getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
LLT) const override;
InstructionMappings
getInstrAlternativeMappings(const MachineInstr &MI) const override;

5
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
View File

@ -177,8 +177,9 @@ unsigned AMDGPURegisterBankInfo::getBreakDownCost(
return 1;
}
const RegisterBank &AMDGPURegisterBankInfo::getRegBankFromRegClass(
const TargetRegisterClass &RC) const {
const RegisterBank &
AMDGPURegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
LLT Ty) const {
if (&RC == &AMDGPU::SReg_1RegClass)
return AMDGPU::VCCRegBank;

4
lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
View File

@ -155,8 +155,8 @@ public:
unsigned getBreakDownCost(const ValueMapping &ValMapping,
const RegisterBank *CurBank = nullptr) const override;
const RegisterBank &
getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
LLT) const override;
InstructionMappings
getInstrAlternativeMappings(const MachineInstr &MI) const override;

5
lib/Target/ARM/ARMRegisterBankInfo.cpp
View File

@ -172,8 +172,9 @@ ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI)
#endif
}
const RegisterBank &ARMRegisterBankInfo::getRegBankFromRegClass(
const TargetRegisterClass &RC) const {
const RegisterBank &
ARMRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
LLT) const {
using namespace ARM;
switch (RC.getID()) {

4
lib/Target/ARM/ARMRegisterBankInfo.h
View File

@ -32,8 +32,8 @@ class ARMRegisterBankInfo final : public ARMGenRegisterBankInfo {
public:
ARMRegisterBankInfo(const TargetRegisterInfo &TRI);
const RegisterBank &
getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
LLT) const override;
const InstructionMapping &
getInstrMapping(const MachineInstr &MI) const override;

5
lib/Target/Mips/MipsRegisterBankInfo.cpp
View File

@ -76,8 +76,9 @@ using namespace llvm;
MipsRegisterBankInfo::MipsRegisterBankInfo(const TargetRegisterInfo &TRI)
: MipsGenRegisterBankInfo() {}
const RegisterBank &MipsRegisterBankInfo::getRegBankFromRegClass(
const TargetRegisterClass &RC) const {
const RegisterBank &
MipsRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
LLT) const {
using namespace Mips;
switch (RC.getID()) {

4
lib/Target/Mips/MipsRegisterBankInfo.h
View File

@ -32,8 +32,8 @@ class MipsRegisterBankInfo final : public MipsGenRegisterBankInfo {
public:
MipsRegisterBankInfo(const TargetRegisterInfo &TRI);
const RegisterBank &
getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
LLT) const override;
const InstructionMapping &
getInstrMapping(const MachineInstr &MI) const override;

5
lib/Target/X86/X86RegisterBankInfo.cpp
View File

@ -40,8 +40,9 @@ X86RegisterBankInfo::X86RegisterBankInfo(const TargetRegisterInfo &TRI)
assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit");
}
const RegisterBank &X86RegisterBankInfo::getRegBankFromRegClass(
const TargetRegisterClass &RC) const {
const RegisterBank &
X86RegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
LLT) const {
if (X86::GR8RegClass.hasSubClassEq(&RC) ||
X86::GR16RegClass.hasSubClassEq(&RC) ||

4
lib/Target/X86/X86RegisterBankInfo.h
View File

@ -64,8 +64,8 @@ private:
public:
X86RegisterBankInfo(const TargetRegisterInfo &TRI);
const RegisterBank &
getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
LLT) const override;
InstructionMappings
getInstrAlternativeMappings(const MachineInstr &MI) const override;