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X86: Now that we have a canonical form for vector integer abs, match it into pabs.
llvm-svn: 180600
This commit is contained in:
Benjamin Kramer
parent
7ce75fb032
commit
11723aa321
@ -5094,6 +5094,16 @@ multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
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Sched<[WriteVecALULd]>;
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}
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// Helper fragments to match sext vXi1 to vXiY.
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def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
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VR128:$src))>;
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def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i32 15)))>;
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def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i32 31)))>;
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def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
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VR256:$src))>;
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def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i32 15)))>;
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def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i32 31)))>;
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let Predicates = [HasAVX] in {
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defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
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int_x86_ssse3_pabs_b_128>, VEX;
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@ -5101,6 +5111,19 @@ let Predicates = [HasAVX] in {
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int_x86_ssse3_pabs_w_128>, VEX;
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defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
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int_x86_ssse3_pabs_d_128>, VEX;
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def : Pat<(xor
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(bc_v2i64 (v16i1sextv16i8)),
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(bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
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(VPABSBrr128 VR128:$src)>;
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def : Pat<(xor
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(bc_v2i64 (v8i1sextv8i16)),
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(bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
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(VPABSWrr128 VR128:$src)>;
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def : Pat<(xor
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(bc_v2i64 (v4i1sextv4i32)),
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(bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
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(VPABSDrr128 VR128:$src)>;
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}
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let Predicates = [HasAVX2] in {
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@ -5110,6 +5133,19 @@ let Predicates = [HasAVX2] in {
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int_x86_avx2_pabs_w>, VEX, VEX_L;
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defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
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int_x86_avx2_pabs_d>, VEX, VEX_L;
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def : Pat<(xor
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(bc_v4i64 (v32i1sextv32i8)),
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(bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
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(VPABSBrr256 VR256:$src)>;
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def : Pat<(xor
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(bc_v4i64 (v16i1sextv16i16)),
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(bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
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(VPABSWrr256 VR256:$src)>;
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def : Pat<(xor
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(bc_v4i64 (v8i1sextv8i32)),
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(bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
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(VPABSDrr256 VR256:$src)>;
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}
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defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
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@ -5119,6 +5155,21 @@ defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
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defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
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int_x86_ssse3_pabs_d_128>;
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let Predicates = [HasSSSE3] in {
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def : Pat<(xor
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(bc_v2i64 (v16i1sextv16i8)),
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(bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
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(PABSBrr128 VR128:$src)>;
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def : Pat<(xor
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(bc_v2i64 (v8i1sextv8i16)),
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(bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
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(PABSWrr128 VR128:$src)>;
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def : Pat<(xor
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(bc_v2i64 (v4i1sextv4i32)),
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(bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
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(PABSDrr128 VR128:$src)>;
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}
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//===---------------------------------------------------------------------===//
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// SSSE3 - Packed Binary Operator Instructions
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//===---------------------------------------------------------------------===//
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@ -1,4 +1,6 @@
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; RUN: llc < %s -march=x86-64 -mcpu=x86-64 | FileCheck %s -check-prefix=SSE2
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; RUN: llc < %s -march=x86-64 -mcpu=corei7 | FileCheck %s -check-prefix=SSSE3
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; RUN: llc < %s -march=x86-64 -mcpu=core-avx2 | FileCheck %s -check-prefix=AVX2
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define <4 x i32> @test1(<4 x i32> %a) nounwind {
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; SSE2: test1:
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@ -7,6 +9,14 @@ define <4 x i32> @test1(<4 x i32> %a) nounwind {
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; SSE2-NEXT: padd
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; SSE2-NEXT: pxor
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; SSE2-NEXT: ret
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; SSSE3: test1:
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; SSSE3: pabsd
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; SSSE3-NEXT: ret
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; AVX2: test1:
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; AVX2: vpabsd
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; AVX2-NEXT: ret
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%tmp1neg = sub <4 x i32> zeroinitializer, %a
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%b = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
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%abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg
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@ -20,36 +30,60 @@ define <4 x i32> @test2(<4 x i32> %a) nounwind {
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; SSE2-NEXT: padd
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; SSE2-NEXT: pxor
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; SSE2-NEXT: ret
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; SSSE3: test2:
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; SSSE3: pabsd
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; SSSE3-NEXT: ret
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; AVX2: test2:
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; AVX2: vpabsd
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; AVX2-NEXT: ret
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%tmp1neg = sub <4 x i32> zeroinitializer, %a
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%b = icmp sge <4 x i32> %a, zeroinitializer
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%abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg
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ret <4 x i32> %abs
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}
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define <4 x i32> @test3(<4 x i32> %a) nounwind {
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define <8 x i16> @test3(<8 x i16> %a) nounwind {
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; SSE2: test3:
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; SSE2: movdqa
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; SSE2-NEXT: psrad $31
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; SSE2-NEXT: psraw $15
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; SSE2-NEXT: padd
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; SSE2-NEXT: pxor
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; SSE2-NEXT: ret
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%tmp1neg = sub <4 x i32> zeroinitializer, %a
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%b = icmp sgt <4 x i32> %a, zeroinitializer
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%abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg
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ret <4 x i32> %abs
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; SSSE3: test3:
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; SSSE3: pabsw
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; SSSE3-NEXT: ret
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; AVX2: test3:
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; AVX2: vpabsw
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; AVX2-NEXT: ret
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%tmp1neg = sub <8 x i16> zeroinitializer, %a
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%b = icmp sgt <8 x i16> %a, zeroinitializer
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%abs = select <8 x i1> %b, <8 x i16> %a, <8 x i16> %tmp1neg
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ret <8 x i16> %abs
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}
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define <4 x i32> @test4(<4 x i32> %a) nounwind {
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define <16 x i8> @test4(<16 x i8> %a) nounwind {
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; SSE2: test4:
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; SSE2: movdqa
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; SSE2-NEXT: psrad $31
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; SSE2: pxor
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; SSE2-NEXT: pcmpgtb
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; SSE2-NEXT: padd
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; SSE2-NEXT: pxor
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; SSE2-NEXT: ret
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%tmp1neg = sub <4 x i32> zeroinitializer, %a
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%b = icmp slt <4 x i32> %a, zeroinitializer
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%abs = select <4 x i1> %b, <4 x i32> %tmp1neg, <4 x i32> %a
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ret <4 x i32> %abs
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; SSSE3: test4:
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; SSSE3: pabsb
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; SSSE3-NEXT: ret
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; AVX2: test4:
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; AVX2: vpabsb
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; AVX2-NEXT: ret
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%tmp1neg = sub <16 x i8> zeroinitializer, %a
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%b = icmp slt <16 x i8> %a, zeroinitializer
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%abs = select <16 x i1> %b, <16 x i8> %tmp1neg, <16 x i8> %a
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ret <16 x i8> %abs
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}
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define <4 x i32> @test5(<4 x i32> %a) nounwind {
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@ -59,8 +93,91 @@ define <4 x i32> @test5(<4 x i32> %a) nounwind {
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; SSE2-NEXT: padd
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; SSE2-NEXT: pxor
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; SSE2-NEXT: ret
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; SSSE3: test5:
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; SSSE3: pabsd
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; SSSE3-NEXT: ret
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; AVX2: test5:
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; AVX2: vpabsd
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; AVX2-NEXT: ret
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%tmp1neg = sub <4 x i32> zeroinitializer, %a
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%b = icmp sle <4 x i32> %a, zeroinitializer
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%abs = select <4 x i1> %b, <4 x i32> %tmp1neg, <4 x i32> %a
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ret <4 x i32> %abs
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}
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define <8 x i32> @test6(<8 x i32> %a) nounwind {
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; SSSE3: test6:
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; SSSE3: pabsd
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; SSSE3: pabsd
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; SSSE3-NEXT: ret
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; AVX2: test6:
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; AVX2: vpabsd %ymm
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; AVX2-NEXT: ret
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%tmp1neg = sub <8 x i32> zeroinitializer, %a
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%b = icmp sgt <8 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
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%abs = select <8 x i1> %b, <8 x i32> %a, <8 x i32> %tmp1neg
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ret <8 x i32> %abs
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}
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define <8 x i32> @test7(<8 x i32> %a) nounwind {
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; SSSE3: test7:
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; SSSE3: pabsd
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; SSSE3: pabsd
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; SSSE3-NEXT: ret
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; AVX2: test7:
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; AVX2: vpabsd %ymm
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; AVX2-NEXT: ret
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%tmp1neg = sub <8 x i32> zeroinitializer, %a
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%b = icmp sge <8 x i32> %a, zeroinitializer
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%abs = select <8 x i1> %b, <8 x i32> %a, <8 x i32> %tmp1neg
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ret <8 x i32> %abs
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}
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define <16 x i16> @test8(<16 x i16> %a) nounwind {
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; SSSE3: test8:
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; SSSE3: pabsw
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; SSSE3: pabsw
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; SSSE3-NEXT: ret
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; AVX2: test8:
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; AVX2: vpabsw %ymm
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; AVX2-NEXT: ret
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%tmp1neg = sub <16 x i16> zeroinitializer, %a
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%b = icmp sgt <16 x i16> %a, zeroinitializer
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%abs = select <16 x i1> %b, <16 x i16> %a, <16 x i16> %tmp1neg
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ret <16 x i16> %abs
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}
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define <32 x i8> @test9(<32 x i8> %a) nounwind {
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; SSSE3: test9:
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; SSSE3: pabsb
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; SSSE3: pabsb
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; SSSE3-NEXT: ret
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; AVX2: test9:
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; AVX2: vpabsb %ymm
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; AVX2-NEXT: ret
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%tmp1neg = sub <32 x i8> zeroinitializer, %a
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%b = icmp slt <32 x i8> %a, zeroinitializer
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%abs = select <32 x i1> %b, <32 x i8> %tmp1neg, <32 x i8> %a
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ret <32 x i8> %abs
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}
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define <8 x i32> @test10(<8 x i32> %a) nounwind {
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; SSSE3: test10:
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; SSSE3: pabsd
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; SSSE3: pabsd
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; SSSE3-NEXT: ret
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; AVX2: test10:
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; AVX2: vpabsd %ymm
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; AVX2-NEXT: ret
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%tmp1neg = sub <8 x i32> zeroinitializer, %a
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%b = icmp sle <8 x i32> %a, zeroinitializer
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%abs = select <8 x i1> %b, <8 x i32> %tmp1neg, <8 x i32> %a
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ret <8 x i32> %abs
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}
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