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Emit proper rounding mode for fp_to_sint
llvm-svn: 76037
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@ -277,20 +277,20 @@ def FCONVFP64 : Pseudo<(outs FP64:$dst), (ins GR64:$src),
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(implicit PSW)]>;
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(implicit PSW)]>;
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def FCONVGR32 : Pseudo<(outs GR32:$dst), (ins FP32:$src),
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def FCONVGR32 : Pseudo<(outs GR32:$dst), (ins FP32:$src),
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"cfebr\t{$dst, $src}",
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"cfebr\t{$dst, 5, $src}",
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[(set GR32:$dst, (fp_to_sint FP32:$src)),
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[(set GR32:$dst, (fp_to_sint FP32:$src)),
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(implicit PSW)]>;
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(implicit PSW)]>;
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def FCONVGR32r64: Pseudo<(outs GR32:$dst), (ins FP64:$src),
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def FCONVGR32r64: Pseudo<(outs GR32:$dst), (ins FP64:$src),
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"cgebr\t{$dst, $src}",
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"cgebr\t{$dst, 5, $src}",
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[(set GR32:$dst, (fp_to_sint FP64:$src)),
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[(set GR32:$dst, (fp_to_sint FP64:$src)),
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(implicit PSW)]>;
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(implicit PSW)]>;
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def FCONVGR64r32: Pseudo<(outs GR64:$dst), (ins FP32:$src),
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def FCONVGR64r32: Pseudo<(outs GR64:$dst), (ins FP32:$src),
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"cfdbr\t{$dst, $src}",
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"cfdbr\t{$dst, 5, $src}",
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[(set GR64:$dst, (fp_to_sint FP32:$src)),
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[(set GR64:$dst, (fp_to_sint FP32:$src)),
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(implicit PSW)]>;
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(implicit PSW)]>;
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def FCONVGR64 : Pseudo<(outs GR64:$dst), (ins FP64:$src),
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def FCONVGR64 : Pseudo<(outs GR64:$dst), (ins FP64:$src),
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"cgdbr\t{$dst, $src}",
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"cgdbr\t{$dst, 5, $src}",
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[(set GR64:$dst, (fp_to_sint FP64:$src)),
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[(set GR64:$dst, (fp_to_sint FP64:$src)),
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(implicit PSW)]>;
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(implicit PSW)]>;
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} // Defs = [PSW]
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} // Defs = [PSW]
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