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[ARM] Allowing SP/PC for AND/BIC mod_imm_not

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AND/BIC instructions do accept SP/PC, so the register class should be
more generic (rGPR -> GPR) to cope with that case. Adding more tests.

llvm-svn: 255034
This commit is contained in:
Renato Golin 2015-12-08 18:10:58 +00:00
parent 4149367a5a
commit 119a82eabd
2 changed files with 15 additions and 4 deletions
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8
lib/Target/ARM/ARMInstrInfo.td
View File

@ -5655,16 +5655,16 @@ def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
(MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
// Same for AND <--> BIC
def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
(ANDri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
(ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
pred:$p, cc_out:$s)>;
def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
(ANDri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
(ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm,
pred:$p, cc_out:$s)>;
def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
(BICri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
(BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
pred:$p, cc_out:$s)>;
def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
(BICri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
(BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm,
pred:$p, cc_out:$s)>;
// Likewise, "add Rd, mod_imm_neg" -> sub

11
test/MC/ARM/basic-arm-instructions.s
View File

@ -349,6 +349,8 @@ Lforward:
and r6, r7, r8, ror r2
and r10, r1, r6, rrx
and r2, r3, #0x7fffffff
and sp, sp, #0x7fffffff
and pc, pc, #0x7fffffff
@ destination register is optional
and r1, #0xf
@ -397,6 +399,8 @@ Lforward:
@ CHECK: and r6, r7, r8, ror r2 @ encoding: [0x78,0x62,0x07,0xe0]
@ CHECK: and r10, r1, r6, rrx @ encoding: [0x66,0xa0,0x01,0xe0]
@ CHECK: bic r2, r3, #-2147483648 @ encoding: [0x02,0x21,0xc3,0xe3]
@ CHECK: bic sp, sp, #-2147483648 @ encoding: [0x02,0xd1,0xcd,0xe3]
@ CHECK: bic pc, pc, #-2147483648 @ encoding: [0x02,0xf1,0xcf,0xe3]
@ CHECK: and r1, r1, #15 @ encoding: [0x0f,0x10,0x01,0xe2]
@ CHECK: and r1, r1, #15 @ encoding: [0x0f,0x10,0x01,0xe2]
@ -502,6 +506,10 @@ Lforward:
bic r6, r7, r8, asr r2
bic r6, r7, r8, ror r2
bic r10, r1, r6, rrx
bic r2, r3, #0x7fffffff
bic sp, sp, #0x7fffffff
bic pc, pc, #0x7fffffff
@ destination register is optional
bic r1, #0xf
@ -548,6 +556,9 @@ Lforward:
@ CHECK: bic r6, r7, r8, asr r2 @ encoding: [0x58,0x62,0xc7,0xe1]
@ CHECK: bic r6, r7, r8, ror r2 @ encoding: [0x78,0x62,0xc7,0xe1]
@ CHECK: bic r10, r1, r6, rrx @ encoding: [0x66,0xa0,0xc1,0xe1]
@ CHECK: and r2, r3, #-2147483648 @ encoding: [0x02,0x21,0x03,0xe2]
@ CHECK: and sp, sp, #-2147483648 @ encoding: [0x02,0xd1,0x0d,0xe2]
@ CHECK: and pc, pc, #-2147483648 @ encoding: [0x02,0xf1,0x0f,0xe2]
@ CHECK: bic r1, r1, #15 @ encoding: [0x0f,0x10,0xc1,0xe3]