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- Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}.
- Fix a small VEX encoding issue. - Move compare instructions to their appropriate place. llvm-svn: 106787
This commit is contained in:
Bruno Cardoso Lopes
parent
7a5bf34236
commit
11a236d970
@ -484,14 +484,6 @@ let Constraints = "$src1 = $dst" in {
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(loadi32 addr:$src2)))]>;
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}
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// Compare Instructions
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let Defs = [EFLAGS] in {
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def COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
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"comiss\t{$src2, $src1|$src1, $src2}", []>;
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def COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
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"comiss\t{$src2, $src1|$src1, $src2}", []>;
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} // Defs = [EFLAGS]
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Move Instructions
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//===----------------------------------------------------------------------===//
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@ -704,97 +696,105 @@ let Constraints = "$src1 = $dst" in {
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// SSE 1 & 2 - Compare Instructions
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//===----------------------------------------------------------------------===//
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multiclass sse12_cmp<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int,
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string asm, Domain d, Operand sse_imm_op> {
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def rri : PIi8<0xC2, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, RC:$src, sse_imm_op:$cc), asm,
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[(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
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def rmi : PIi8<0xC2, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, f128mem:$src, sse_imm_op:$cc), asm,
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[(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
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}
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// FIXME: rename instructions to only use the class above
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multiclass sse12_cmp_alt<RegisterClass RC, string asm, Domain d,
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Operand sse_imm_op> {
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def rri_alt : PIi8<0xC2, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, RC:$src, sse_imm_op:$src2), asm,
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[], d>;
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def rmi_alt : PIi8<0xC2, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, f128mem:$src, sse_imm_op:$src2), asm,
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[], d>;
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}
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// sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
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multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
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Operand sse_imm_op, string asm> {
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string asm, string asm_alt> {
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def rr : SIi8<0xC2, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, RC:$src, sse_imm_op:$cc),
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(outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
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asm, []>;
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let mayLoad = 1 in
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def rm : SIi8<0xC2, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, x86memop:$src, sse_imm_op:$cc),
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asm, []>;
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}
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// FIXME: rename instructions to only use the class above
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multiclass sse12_cmp_scalar_alt<RegisterClass RC, X86MemOperand x86memop,
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Operand sse_imm_op, string asm> {
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def rr_alt : SIi8<0xC2, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, RC:$src, sse_imm_op:$src2),
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asm, []>;
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let mayLoad = 1 in
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def rm_alt : SIi8<0xC2, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, x86memop:$src, sse_imm_op:$src2),
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(outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
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asm, []>;
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// Accept explicit immediate argument form instead of comparison code.
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let isAsmParserOnly = 1 in {
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def rr_alt : SIi8<0xC2, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
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asm_alt, []>;
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let mayLoad = 1 in
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def rm_alt : SIi8<0xC2, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
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asm_alt, []>;
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}
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}
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let neverHasSideEffects = 1, isAsmParserOnly = 1 in {
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defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC,
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"cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
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XS, VEX_4V;
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defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC,
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"cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
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XD, VEX_4V;
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// Accept explicit immediate argument form instead of comparison code.
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let isAsmParserOnly = 1 in {
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defm VCMPSS : sse12_cmp_scalar_alt<FR32, f32mem, i8imm,
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"cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
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XS, VEX_4V;
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defm VCMPSD : sse12_cmp_scalar_alt<FR64, f32mem, i8imm,
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"cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
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XD, VEX_4V;
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}
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defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
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"cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
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"cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
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XS, VEX_4V;
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defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
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"cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
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"cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
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XD, VEX_4V;
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}
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let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
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defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC,
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"cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
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defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC,
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"cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
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defm CMPSS : sse12_cmp_scalar<FR32, f32mem,
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"cmp${cc}ss\t{$src, $dst|$dst, $src}",
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"cmpss\t{$src2, $src, $dst|$dst, $src, $src2}">, XS;
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defm CMPSD : sse12_cmp_scalar<FR64, f64mem,
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"cmp${cc}sd\t{$src, $dst|$dst, $src}",
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"cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}">, XD;
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}
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// Accept explicit immediate argument form instead of comparison code.
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let isAsmParserOnly = 1 in {
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defm CMPSS : sse12_cmp_scalar_alt<FR32, f32mem, i8imm,
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"cmpss\t{$src2, $src, $dst|$dst, $src, $src2}">, XS;
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defm CMPSD : sse12_cmp_scalar_alt<FR64, f32mem, i8imm,
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"cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}">, XD;
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}
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// sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
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multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
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ValueType vt, X86MemOperand x86memop,
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PatFrag ld_frag, string OpcodeStr, Domain d> {
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def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
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[(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
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def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
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[(set EFLAGS, (OpNode (vt RC:$src1),
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(ld_frag addr:$src2)))], d>;
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}
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let Defs = [EFLAGS] in {
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def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
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"ucomiss\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86cmp FR32:$src1, FR32:$src2))]>;
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def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
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"ucomiss\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86cmp FR32:$src1, (loadf32 addr:$src2)))]>;
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def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
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"ucomisd\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86cmp FR64:$src1, FR64:$src2))]>;
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def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
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"ucomisd\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86cmp FR64:$src1, (loadf64 addr:$src2)))]>;
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let isAsmParserOnly = 1 in {
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defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
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"ucomiss", SSEPackedSingle>, VEX;
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defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
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"ucomisd", SSEPackedDouble>, OpSize, VEX;
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let Pattern = []<dag> in {
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defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
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"comiss", SSEPackedSingle>, VEX;
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defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
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"comisd", SSEPackedDouble>, OpSize, VEX;
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}
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defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
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load, "ucomiss", SSEPackedSingle>, VEX;
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defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
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load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
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defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
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load, "comiss", SSEPackedSingle>, VEX;
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defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
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load, "comisd", SSEPackedDouble>, OpSize, VEX;
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}
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defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
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"ucomiss", SSEPackedSingle>, TB;
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defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
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"ucomisd", SSEPackedDouble>, TB, OpSize;
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let Pattern = []<dag> in {
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defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
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"comiss", SSEPackedSingle>, TB;
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defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
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"comisd", SSEPackedDouble>, TB, OpSize;
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}
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defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
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load, "ucomiss", SSEPackedSingle>, TB;
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defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
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load, "ucomisd", SSEPackedDouble>, TB, OpSize;
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defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
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"comiss", SSEPackedSingle>, TB;
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defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
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"comisd", SSEPackedDouble>, TB, OpSize;
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} // Defs = [EFLAGS]
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// Aliases to match intrinsics which expect XMM operand(s).
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@ -827,75 +827,46 @@ let Constraints = "$src1 = $dst" in {
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(load addr:$src), imm:$cc))]>;
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}
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let Defs = [EFLAGS] in {
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def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
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"ucomiss\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
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VR128:$src2))]>;
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def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
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"ucomiss\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
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(load addr:$src2)))]>;
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def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
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"ucomisd\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
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VR128:$src2))]>;
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def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
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"ucomisd\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
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(load addr:$src2)))]>;
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def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
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"comiss\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86comi (v4f32 VR128:$src1),
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VR128:$src2))]>;
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def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
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"comiss\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86comi (v4f32 VR128:$src1),
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(load addr:$src2)))]>;
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def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
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"comisd\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86comi (v2f64 VR128:$src1),
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VR128:$src2))]>;
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def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
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"comisd\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86comi (v2f64 VR128:$src1),
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(load addr:$src2)))]>;
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} // Defs = [EFLAGS]
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let Constraints = "$src1 = $dst" in {
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defm CMPPS : sse12_cmp<VR128, f128mem, int_x86_sse_cmp_ps,
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"cmp${cc}ps\t{$src, $dst|$dst, $src}", SSEPackedSingle, SSECC>,
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TB;
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defm CMPPD : sse12_cmp<VR128, f128mem, int_x86_sse2_cmp_pd,
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"cmp${cc}pd\t{$src, $dst|$dst, $src}", SSEPackedDouble, SSECC>,
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TB, OpSize;
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}
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let isAsmParserOnly = 1 in {
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defm VCMPPS : sse12_cmp<VR128, f128mem, int_x86_sse_cmp_ps,
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"cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
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SSEPackedSingle, SSECC>, VEX_4V;
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defm VCMPPD : sse12_cmp<VR128, f128mem, int_x86_sse2_cmp_pd,
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"cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
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SSEPackedSingle, SSECC>, OpSize, VEX_4V;
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}
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let isAsmParserOnly = 1, Pattern = []<dag> in {
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// sse12_cmp_packed - sse 1 & 2 compared packed instructions
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multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
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Intrinsic Int, string asm, string asm_alt,
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Domain d> {
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def rri : PIi8<0xC2, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
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[(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
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def rmi : PIi8<0xC2, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
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[(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
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// Accept explicit immediate argument form instead of comparison code.
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let Constraints = "$src1 = $dst" in {
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defm CMPPS : sse12_cmp_alt<VR128,
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"cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
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SSEPackedSingle, i8imm>, TB;
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defm CMPPD : sse12_cmp_alt<VR128,
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"cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
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SSEPackedDouble, i8imm>, TB, OpSize;
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let isAsmParserOnly = 1 in {
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def rri_alt : PIi8<0xC2, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
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asm_alt, [], d>;
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def rmi_alt : PIi8<0xC2, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
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asm_alt, [], d>;
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}
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defm VCMPPS : sse12_cmp_alt<VR128,
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"cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src}",
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SSEPackedSingle, i8imm>, VEX_4V;
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defm VCMPPD : sse12_cmp_alt<VR128,
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}
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let isAsmParserOnly = 1 in {
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defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
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"cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
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"cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
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SSEPackedSingle>, VEX_4V;
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defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
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"cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
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"cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
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SSEPackedSingle, i8imm>, OpSize, VEX_4V;
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SSEPackedDouble>, OpSize, VEX_4V;
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}
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let Constraints = "$src1 = $dst" in {
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defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
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"cmp${cc}ps\t{$src, $dst|$dst, $src}",
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"cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
|
||||
SSEPackedSingle>, TB;
|
||||
defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
|
||||
"cmp${cc}pd\t{$src, $dst|$dst, $src}",
|
||||
"cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
|
||||
SSEPackedDouble>, TB, OpSize;
|
||||
}
|
||||
|
||||
def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
|
||||
@ -1599,10 +1570,6 @@ def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"cvtps2dq\t{$src, $dst|$dst, $src}", []>;
|
||||
def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
||||
"cvtps2dq\t{$src, $dst|$dst, $src}", []>;
|
||||
def COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
|
||||
"comisd\t{$src2, $src1|$src1, $src2}", []>;
|
||||
def COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
|
||||
"comisd\t{$src2, $src1|$src1, $src2}", []>;
|
||||
|
||||
// SSE2 instructions with XS prefix
|
||||
def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
|
||||
|
||||
@ -364,6 +364,10 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
|
||||
if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
|
||||
return;
|
||||
|
||||
bool HasVEX_4V = false;
|
||||
if ((TSFlags >> 32) & X86II::VEX_4V)
|
||||
HasVEX_4V = true;
|
||||
|
||||
// VEX_R: opcode externsion equivalent to REX.R in
|
||||
// 1's complement (inverted) form
|
||||
//
|
||||
@ -447,8 +451,7 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
|
||||
}
|
||||
|
||||
unsigned NumOps = MI.getNumOperands();
|
||||
unsigned i = 0;
|
||||
unsigned SrcReg = 0, SrcRegNum = 0;
|
||||
unsigned i = 0, CurOp = 0;
|
||||
bool IsSrcMem = false;
|
||||
|
||||
switch (TSFlags & X86II::FormMask) {
|
||||
@ -456,9 +459,10 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
|
||||
case X86II::MRMSrcMem:
|
||||
IsSrcMem = true;
|
||||
case X86II::MRMSrcReg:
|
||||
if (MI.getOperand(0).isReg() &&
|
||||
X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
|
||||
if (MI.getOperand(CurOp).isReg() &&
|
||||
X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
|
||||
VEX_R = 0x0;
|
||||
CurOp++;
|
||||
|
||||
// On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the
|
||||
// range 0-7 and the difference between the 2 groups is given by the
|
||||
@ -469,17 +473,20 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
|
||||
// VEX.VVVV => XMM9 => ~9
|
||||
//
|
||||
// See table 4-35 of Intel AVX Programming Reference for details.
|
||||
SrcReg = MI.getOperand(1).getReg();
|
||||
SrcRegNum = GetX86RegNum(MI.getOperand(1));
|
||||
if (SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15)
|
||||
SrcRegNum += 8;
|
||||
if (HasVEX_4V) {
|
||||
unsigned SrcReg = MI.getOperand(CurOp).getReg();
|
||||
unsigned SrcRegNum = GetX86RegNum(MI.getOperand(1));
|
||||
if (SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15)
|
||||
SrcRegNum += 8;
|
||||
|
||||
// The registers represented through VEX_VVVV should
|
||||
// be encoded in 1's complement form.
|
||||
if ((TSFlags >> 32) & X86II::VEX_4V)
|
||||
// The registers represented through VEX_VVVV should
|
||||
// be encoded in 1's complement form.
|
||||
VEX_4V = (~SrcRegNum) & 0xf;
|
||||
|
||||
i = 2; // Skip the VEX.VVVV operand.
|
||||
CurOp++;
|
||||
}
|
||||
|
||||
i = CurOp;
|
||||
for (; i != NumOps; ++i) {
|
||||
const MCOperand &MO = MI.getOperand(i);
|
||||
if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
|
||||
|
||||
@ -10654,3 +10654,35 @@
|
||||
// CHECK: encoding: [0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x03]
|
||||
vcmpunordsd -4(%ebx,%ecx,8), %xmm2, %xmm3
|
||||
|
||||
// CHECK: vucomiss %xmm1, %xmm2
|
||||
// CHECK: encoding: [0xc5,0xf8,0x2e,0xd1]
|
||||
vucomiss %xmm1, %xmm2
|
||||
|
||||
// CHECK: vucomiss (%eax), %xmm2
|
||||
// CHECK: encoding: [0xc5,0xf8,0x2e,0x10]
|
||||
vucomiss (%eax), %xmm2
|
||||
|
||||
// CHECK: vcomiss %xmm1, %xmm2
|
||||
// CHECK: encoding: [0xc5,0xf8,0x2f,0xd1]
|
||||
vcomiss %xmm1, %xmm2
|
||||
|
||||
// CHECK: vcomiss (%eax), %xmm2
|
||||
// CHECK: encoding: [0xc5,0xf8,0x2f,0x10]
|
||||
vcomiss (%eax), %xmm2
|
||||
|
||||
// CHECK: vucomisd %xmm1, %xmm2
|
||||
// CHECK: encoding: [0xc5,0xf9,0x2e,0xd1]
|
||||
vucomisd %xmm1, %xmm2
|
||||
|
||||
// CHECK: vucomisd (%eax), %xmm2
|
||||
// CHECK: encoding: [0xc5,0xf9,0x2e,0x10]
|
||||
vucomisd (%eax), %xmm2
|
||||
|
||||
// CHECK: vcomisd %xmm1, %xmm2
|
||||
// CHECK: encoding: [0xc5,0xf9,0x2f,0xd1]
|
||||
vcomisd %xmm1, %xmm2
|
||||
|
||||
// CHECK: vcomisd (%eax), %xmm2
|
||||
// CHECK: encoding: [0xc5,0xf9,0x2f,0x10]
|
||||
vcomisd (%eax), %xmm2
|
||||
|
||||
|
||||
@ -710,3 +710,36 @@ pshufb CPI1_0(%rip), %xmm1
|
||||
// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x03]
|
||||
vcmpunordsd -4(%rbx,%rcx,8), %xmm12, %xmm13
|
||||
|
||||
// CHECK: vucomiss %xmm11, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x41,0x78,0x2e,0xe3]
|
||||
vucomiss %xmm11, %xmm12
|
||||
|
||||
// CHECK: vucomiss (%rax), %xmm12
|
||||
// CHECK: encoding: [0xc5,0x78,0x2e,0x20]
|
||||
vucomiss (%rax), %xmm12
|
||||
|
||||
// CHECK: vcomiss %xmm11, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x41,0x78,0x2f,0xe3]
|
||||
vcomiss %xmm11, %xmm12
|
||||
|
||||
// CHECK: vcomiss (%rax), %xmm12
|
||||
// CHECK: encoding: [0xc5,0x78,0x2f,0x20]
|
||||
vcomiss (%rax), %xmm12
|
||||
|
||||
// CHECK: vucomisd %xmm11, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x41,0x79,0x2e,0xe3]
|
||||
vucomisd %xmm11, %xmm12
|
||||
|
||||
// CHECK: vucomisd (%rax), %xmm12
|
||||
// CHECK: encoding: [0xc5,0x79,0x2e,0x20]
|
||||
vucomisd (%rax), %xmm12
|
||||
|
||||
// CHECK: vcomisd %xmm11, %xmm12
|
||||
// CHECK: encoding: [0xc4,0x41,0x79,0x2f,0xe3]
|
||||
vcomisd %xmm11, %xmm12
|
||||
|
||||
// CHECK: vcomisd (%rax), %xmm12
|
||||
// CHECK: encoding: [0xc5,0x79,0x2f,0x20]
|
||||
vcomisd (%rax), %xmm12
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user